초록 ▼

Integrated circuit models having associated timing and tag information therewith for use with design optimizations to effectively model timing exception information. The present invention includes a circuit block model which allows automated circuit optimization to be performed on extremely large ci

Integrated circuit models having associated timing and tag information therewith for use with design optimizations to effectively model timing exception information. The present invention includes a circuit block model which allows automated circuit optimization to be performed on extremely large circuits without the need to load all of the details of the circuit into computer memory. The circuit models of the present invention effectively model timing including timing exception information. The model of the present invention is associated with command information, e.g., textual commands, that describe tags (which model exceptions) and arrival and required times associated with the tags. Specifically, for the input pins of a circuit to be modeled, the present invention writes out a command defining each unique required tag associated with an input pin and also writes out commands associating each required tag with its input pin. For the output pins of a circuit to be modeled, the present invention writes out a command defining each unique arrival tag associated with an output pin and also writes out commands associating each arrival tag with its output pin. The tag, arrival and required information is then associated with the model. Timing exceptions are thereby effectively and efficiently modeled using this process. The present invention also includes various circuit optimization processes that utilize the above described circuit model with command information. These circuit optimizations can be used for incremental optimization of a large circuit.

대표청구항 ▼

1. A method of optimizing an integrated circuit design comprising the steps of:a) accessing said integrated circuit design comprising circuit models for representing corresponding circuit blocks, wherein a circuit model comprises: first commands which are definitions that correspond to timing except

1. A method of optimizing an integrated circuit design comprising the steps of:a) accessing said integrated circuit design comprising circuit models for representing corresponding circuit blocks, wherein a circuit model comprises: first commands which are definitions that correspond to timing exception paths that cross the boundary of a circuit block that corresponds to said circuit model; and second commands that associate respective boundary pins of said circuit model with timing values defined for said respective boundary pins and wherein said timing values reference said definitions of said first commands; and b) optimizing said integrated circuit design having said circuit models to improve characteristics of said integrated circuit design.