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A system is disclosed including a reconfigurable logic circuit having programmable logic, a first memory, and a second memory. The first memory stores a number of logic designs each operable to configure the programmable logic. Also included is a computer coupled to the reconfigurable logic circuit

A system is disclosed including a reconfigurable logic circuit having programmable logic, a first memory, and a second memory. The first memory stores a number of logic designs each operable to configure the programmable logic. Also included is a computer coupled to the reconfigurable logic circuit that concurrently executes one or more application programs and an interface program. The application programs generate a number of requests to utilize the reconfigurable logic circuit and the interface program responds to the requests by opening a number of coexisting program interfaces. These interfaces each correspond to an instance of one of the logic designs stored in the first memory. The reconfigurable logic circuit is responsive to the interface program to provide a number of interface buffers in the second memory that each belong to a corresponding one of the interfaces and are each operable to store data passing between the computer and the reconfigurable logic circuit.

대표청구항 ▼

1. A system comprising:a reconfigurable logic circuit including programmable logic, a first memory and a second memory, said first memory being arranged to store a number of logic designs each operable to configure said programmable logic; a computer coupled to said reconfigurable logic circuit, sai

1. A system comprising:a reconfigurable logic circuit including programmable logic, a first memory and a second memory, said first memory being arranged to store a number of logic designs each operable to configure said programmable logic; a computer coupled to said reconfigurable logic circuit, said computer being operable to concurrently execute one or more application programs and an interface program, the one or more application programs generating a number of requests to utilize said reconfigurable logic circuit, the interface program being responsive to the requests to open a number of coexisting program interfaces between the one or more application programs and said reconfigurable logic circuit, the program interfaces each corresponding to one of the logic designs stored in said first memory; wherein the reconfigurable logic circuit, in response to the interface program, provides a number of interface buffers in the second memory, each interface buffer corresponding to one of the program interfaces; and wherein each provided interface buffer is operable to store data passing between the computer and the reconfigurable logic circuit.