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Process of producing plastic pin grid array 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01R-043/20
출원번호 US-0292163 (1999-04-15)
발명자 / 주소
  • Eric P. Dibble
  • Eric H. Laine
  • Stephen W. MacQuarrie
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    RatnerPrestia
인용정보 피인용 횟수 : 4  인용 특허 : 36

초록

A pinning process including the steps of gold-plating through-holes in a laminate carrier and crimping old or gold-plated pin located in the through-holes to form a pin head on the top and a pin bulge on the bottom of the laminate carrier to produce a plastic pin grid array. A variety of mechanical

대표청구항

1. A method for making a plastic pin grid array comprising a circuitized laminate carrier having a top surface and a bottom surface, a centrally disposed dielectric material, and at least one transverse through-hole which defines an inner-surface with a corresponding at least one solid pin inserted

이 특허에 인용된 특허 (36)

  1. Locke Barbara E. (Deep River CT) Burdick Lynn E. (Hampton CT) Owens Mark J. (Phoenix AZ) St. Lawrence Michael (Thompson CT) Simpson Scott S. (Woodstock CT), Array connector.
  2. Legrady Janos ; Fredriks Ronald M., Capillary action promoting surface mount connectors.
  3. Sitzler Fred C. (Hanover PA), Circuit board contact element and compliant section thereof.
  4. Bianca Giuseppe ; Bogursky Robert M., Conforming press-fit contact pin for printed circuit board.
  5. Yamasaki Kozo,JPX ; Saiki Hajime,JPX, Connecting board for connection between base plate and mounting board.
  6. Rogers Wesley D. (Huntsville AL) Hard Douglas G. (Fayetteville TN), Cross-connect system.
  7. Nye ; III Henry A. (Bedford NY) Roeder Jeffrey F. (Brookfield CT) Tong Ho-Ming (Yorktown Heights NY) Totta Paul A. (Poughkeepsie NY), Electroplated solder terminal.
  8. Cray Seymour R. (Chippewa Falls WI) Krajewski Nicholas J. (Elk Mound WI), Flying leads for integrated circuits.
  9. Cohn Charles (Wayne NJ), Integrated circuit package using plastic encapsulant.
  10. Lee James C. K. (Los Altos Hills CA), Integrated circuit packaging systems with double surface heat dissipation.
  11. Cray Seymour R. (Chippewa Falls WI) Krajewski Nicholas J. (Elk Mound WI), Lead bonding of chips to circuit boards and circuit boards to circuit boards.
  12. Saban John F. (Lyons IL), Lead-receiving socket, multi-socket assembly incorporating same and method of effecting circuit interconnections therewi.
  13. Jones ; II Kenneth L. (Escondido CA) O\Connor Tom R. (San Marcos CA) Trevellyan Kenneth A. (San Diego CA), Low cost, hermetic pin grid array package.
  14. Kuraishi Fumio,JPX ; Yoda Toshihisa,JPX ; Shimizu Mitsuharu,JPX, Method for producing a semiconductor package.
  15. Chobot Ivan Ivor,CAX ; Covert John Arthur ; Haight Randy Lee ; Mansfield Keith David ; Miller Donald Wayne ; Neira Reinaldo Anthony ; Petrovich Alexander ; Sviedrys Paul Camilo ; Tiemann Louise Ann ;, Method of forming electronic multilayer printed circuit boards or cards.
  16. Ohno Jun-ichi (Yokohama JPX) Fukazawa Koh-ichi (Tokyo JPX) Shindo Masamichi (Yokohama JPX), Method of making a semiconductor device having lead pins and a metal shell.
  17. Grabbe Dimitry G. (Middletown PA) Korsunsky Iosif (Harrisburg PA), Method of making contact surface for contact element.
  18. Komathu Kathuzi (Kawagoe JPX), Method of molding a protective cover on a pin grid array.
  19. Chia Chok J. (Santa Clara CA), Molded pin grid array package GPT.
  20. Huang Chin-Ching (San Jose CA) Lee Sang S. (Sunnyvale CA) Rao Ramachandra A. (Pleasanton CA) Forcier ; Jr. Fernand N. (San Jose CA), Multi-layered, integrated circuit package having reduced parasitic noise characteristics.
  21. Currie Thomas P. (St. Paul MN) Goldberg Norman (Dresher PA), Multichip thin film module.
  22. McShane Michael B. (Austin TX) Lin Paul T. (Austin TX) Wilson Howard P. (Austin TX), Packaged semiconductor device having a low cost ceramic PGA package.
  23. Dibble Eric P. ; Laine Eric H. ; MacQuarrie Stephen W., Pin attach structure for an electronic package.
  24. Bronson Lance A. (Port Crane NY) Moore Scott P. (Apalachin NY) Shriver ; III John A. (Owego NY), Pinned ceramic chip carrier.
  25. Theobald Paul R. (Signal Mountain TN), Plastic chip carrier package.
  26. Muehling Richard (Cranston RI), Plastic pin grid array chip carrier.
  27. Cohn Charles (Wayne NJ), Plastic pin grid array package.
  28. Lin Paul T. (Austin TX), Process for making a hermetic low cost pin grid array package.
  29. Bridges William G. (Meriden CT) Armer Thomas A. (New Haven CT) Chang Kin-Shiung (Meriden CT), Process for manufacturing plastic pin grid arrays and the product produced thereby.
  30. Chia Chok J. ; Lim Seng-Sooi ; Variot Patrick, Programmable substrate for array-type packages.
  31. Konishi Akira (Kyoto JPX) Wakano Teruo (Kyoto JPX), Semiconductor device and its manufacture.
  32. Sugimoto Masahiro (Yokosuka JPX) Wakasugi Yasumasa (Kawasaki JPX) Harada Shigeki (Kawasaki JPX), Semiconductor device and method of producing semiconductor device.
  33. Fukuda Masatoshi,JPX, Semiconductor device substrate and method of manufacturing the same.
  34. Takeda Yoshiki,JPX ; Machida Takemi,JPX ; Kuraishi Fumio,JPX, Semiconductor package having a heat slug.
  35. Grabbe Dimitry G. (Middletown PA) Granitz Richard F. (Harrisburg PA), Surface mounting an electronic component.
  36. Grabow Wilhelm (Nordstemmen DEX) Bode Friedrich-Wilhelm (Apelern DEX), System for bidirectional data transmission between a beacon and a vehicle.

이 특허를 인용한 특허 (4)

  1. Magnuson, Roy H.; Markovich, Voya R.; Miller, Thomas R.; Wozniak, Michael, Copper plated PTH barrels and methods for fabricating.
  2. Tsai, Chung-Che; Bai, Jin-Chuan, Fabrication method of circuit board.
  3. Oh, Heung Jae; Lee, Ki Taek; Lee, Dong Gyu; Jeong, Sung Won; Choi, Jin Won, Lead pin for package substrate.
  4. Yoshida, Yoshifumi, Method of manufacturing a piezoelectric vibrator.
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