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Interactive instruction scheduling and block ordering 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/45
출원번호 US-0185422 (1998-11-03)
발명자 / 주소
  • Christopher M. McKinsey
  • Jayashankar Bharadwaj
출원인 / 주소
  • Intle Corporation
대리인 / 주소
    Alan K. Aldous
인용정보 피인용 횟수 : 28  인용 특허 : 20

초록

In some embodiments, the invention includes a method of compiling instructions of a program. The method includes receiving instructions for code motion and controlling the code motion while interacting with block ordering. The code motion may be done as part of various activities including instructi

대표청구항

1. A method of compiling instructions of a program, comprising:receiving instructions for code motion; and controlling the code motion while interacting with block ordering, wherein the controlling includes: (a) establishing a physical order before the code motion, wherein the blocks include populat

이 특허에 인용된 특허 (20)

  1. Click ; Jr. Cliff N., Automatic scheduling of instructions to reduce code size.
  2. Odani Kensuke,JPX ; Tanaka Akira,JPX ; Tanaka Hirohisa,JPX, Compiler for optimizing memory instruction sequences by marking instructions not having multiple memory address paths.
  3. Schmidt William J. ; Roediger Robert R., Compiler with extended redundant copy elimination.
  4. Hayashi Masakazu,JPX, Compiling apparatus and method for promoting an optimization effect of a program.
  5. Van Dyke Don A. (Pleasanton CA) Cramer Timothy J. (Pleasanton CA) Rasbold James C. (Livermore CA) O\Hair Kelly T. (Livermore CA) Cox David M. (Livermore CA) Seberger David A. (Livermore CA) O\Gara Li, Computer with integrated hierarchical representation (IHR) of program wherein IHR file is available for debugging and op.
  6. Schlansker Michael S. ; Kathail Vinod, Flexible scheduling of non-speculative instructions.
  7. Bharadwaj Jayashankar, Method and apparatus for instruction scheduling to reduce negative effects of compensation code.
  8. Wallace David R., Method and apparatus for profile-based code placement using a minimum cut set of the control flow graph.
  9. Auslander Marc A. (Millwood NY) Cocke John (Bedford NY) Markstein Peter W. (Yorktown Heights NY), Method for improving global common subexpression elimination and code motion in an optimizing compiler.
  10. Adl-Tabatabai Ali-Reza, Method for performing dynamic optimization of computer code.
  11. Ng John Shek-Luen, Method of, system for, and computer program product for providing improved code motion and code redundancy removal using extended global value numbering.
  12. Lo Raymond ; Chow Frederick, Method, system, and computer program product for extending sparse partial redundancy elimination to support speculative code motion within an optimizing compiler.
  13. Chow Frederick ; Kennedy Robert ; Liu Shin-Ming ; Lo Raymond ; Tu Peng ; Chan Sun C., Method, system, and computer program product for performing register promotion via load and store placement optimization within an optimizing compiler.
  14. Donovan Robert John ; Roediger Robert Ralph ; Schmidt William Jon, Profile driven optimization of frequently executed paths with inlining of code fragment (one or more lines of code from a child procedure to a parent procedure).
  15. Bharadwaj Jayashankar, Representation of control flow and data dependence for machine.
  16. Schmidt William Jon, Skip list data storage during compilation.
  17. Chan Sun C. (Fremont CA) Dehnert James C. (Palo Alto CA) Lo Raymond W. (Sunnyvale CA) Towle Ross A. (San Francisco CA), System and method of generating object code using aggregate instruction movement.
  18. Simons Barbara Bluestein ; Sarkar Vivek, System, method, and program product for instruction scheduling in the presence of hardware lookahead accomplished by th.
  19. Simons Barbara Bluestein ; Sarkar Vivek, System, method, and program product for loop instruction scheduling hardware lookahead.
  20. Ju Dz-Ching, Unified compiler framework for control and data speculation with recovery code.

이 특허를 인용한 특허 (28)

  1. Gillies,David Mitford; Chaiken,Ronnie Ira, Assigning free register to unmaterialized predicate in inverse predicate expression obtained for branch reversal in predicated execution system.
  2. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
  3. Thompson, Carol L., Compiler with flexible scheduling.
  4. Wong, Henry, Compressing dependency graphs in a social network.
  5. Kahle, James Allan; Moore, Charles Roberts, Converting short branches to predicated instructions.
  6. Robison,Arch D., Data-flow method for optimizing exception-handling instructions in programs.
  7. Gillies,David Mitford; Chaiken,Ronnie Ira, Determining guarding predicate from partition graph based deduction to generate inverse predicate expression for branch reversal.
  8. Saito, Kazuo; Kamei, Mitsuhisa; Ishima, Hiroyuki, Execution program generation method, execution program generation apparatus, execution program execution method, and computer-readable storage medium.
  9. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  10. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  11. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  12. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
  13. Chipman, Timothy, Method and system for program transformation using flow-sensitive type constraint analysis.
  14. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  15. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  16. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  17. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  18. Gillies, David Mitford; Chaiken, Ronnie Ira, Method for binary-level branch reversal on computer architectures supporting predicated execution.
  19. Hill, Ralph D., Method for estimating cost when placing operations within a modulo scheduler when scheduling for processors with a large number of function units or reconfigurable data paths.
  20. Hill,Ralph D., Method for estimating cost when placing operations within a modulo scheduler when scheduling for processors with a large number of function units or reconfigurable data paths.
  21. Martin, Allan Russell, Pinning internal slack nodes to improve instruction scheduling.
  22. Martin,Allan Russell, Pinning internal slack nodes to improve instruction scheduling.
  23. Van De Waerdt, Jan-Willem; Roos, Steven, Pipelined processor and compiler/scheduler for variable number branch delay slots.
  24. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
  25. Chipman, Timothy, Program transformation using flow-sensitive type constraint analysis.
  26. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
  27. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
  28. Bharadwaj,Jayashankar; Narayanaswamy,Ravi, User transparent continuous compilation.
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