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Method and apparatus for random stimulus generation 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G01R-031/28
  • G06F-011/00
출원번호 US-0298981 (1999-04-22)
발명자 / 주소
  • Won Sub Kim
  • Mary Lynn Meyer
  • Daniel Marcos Chapiro
출원인 / 주소
  • Synopsys, Inc.
대리인 / 주소
    Jonathan T. Kaplan
인용정보 피인용 횟수 : 16  인용 특허 : 30

초록

The present invention adds capabilities to a Hardware Verification Language (HVL) which facilitate the generation of random test data. Sources of random numbers are easily produced by simply adding a randomness attribute to a variable declaration of a class definition. Such variables are called rand

대표청구항

1. A method for generating values, comprising:generating a graph data structure representing a dependency relation, determined by at least one declarative constraint, between at least a first and a second value generator; generating a linear ordering, from the graph data structure, such that the fir

이 특허에 인용된 특허 (30)

  1. Beck Ronald R. (Banks OR) Stanbro Michael E. (Tigard OR) Thomsen Eric J. (Aloha OR), Circuit verification accessory.
  2. Dangelo J. Carlos ; Nagasamy Vijay, Computer system and method for performing design automation in a distributed computing environment.
  3. Stapleton Warren G., Design for a simulation module using an object-oriented programming language.
  4. Baker Michelle, Diagnostic system utilizing a Bayesian network model having link weights updated experimentally.
  5. Lowe Mike ; Berndt Paul ; Askar Tahsin ; Rendon Enrique, Dynamic configuration of a device under test.
  6. Aharon Aharon (Doar Na Misgav) Bar-David Ayal (Haifa) Gewirtzman Raanan (Haifa) Gofman Emanuel (Haifa) Leibowitz Moshe (Haifa) Shwartzburd Victor (Haifa ILX), Dynamic process for the generation of biased pseudo-random test patterns for the functional verification of hardware des.
  7. Russell Richard G., General purpose dynamically programmable state engine for executing finite state machines.
  8. Jennings Roger H., Generation of multiple simultaneous random test cycles for hardware verification of multiple functions of a design under test.
  9. Peters Michael J., Integrated circuit test stimulus verification and vector extraction system.
  10. Baydar Ertugrul ; Boudreaux J. Bradley ; Carter Nicholas ; Chen Chung ; Klonsky Steven ; Moran Michael ; Renucci Peter ; Timbs Jeffrey ; Tucker Thomas ; Wardak Waleed, Integrated digital loop carrier system with virtual tributary mapper circuit.
  11. Sample Stephen P. ; Bershteyn Mikhail, Method and apparatus for design verification using emulation and simulation.
  12. Cheng Kwang-Ting (Santa Barbara CA) Krishnakumar Anjur S. (Rocky Hill NJ), Method and apparatus for determining the reachable states in a hybrid model state machine.
  13. Kita Ronald Allen ; Trumpler Mark Edward ; Elkind Lois Scirocco, Method and apparatus for generating an extended finite state machine architecture for a software specification.
  14. Albee Alan J. (Nashua NH) Duus Erik (Acton MA) Ellis Mark (Sudbury MA), Method and apparatus for pin assignment in automatic circuit testers.
  15. Hollander Yoav,ILX, Method and apparatus for test generation during circuit design.
  16. Kinzelman Paul M. (Hudson MA) Warchol Nicholas A. (Boxborough MA), Method for control of random test vector generation.
  17. Gregory Brent L. (Sunnyvale CA) Segal Russell B. (Mountain View CA), Method for converting a hardware independent user description of a logic circuit into hardware components.
  18. Jain Prem P., Method for graphically representing a digital device as a behavioral description with data and control flow elements, and for converting the behavioral description to a structural description.
  19. Ashar Pranav N ; Gupta Aarti ; Malik Sharad, Method for using complete-1-distinguishability for FSM equivalence checking.
  20. Puri Ruchir (Calgary CAX) Gu Jun (Calgary CAX), Methodology and apparatus for modular partitioning for the machine design of asynchronous circuits.
  21. Pfluger Thomas,DEX ; Schubert Klaus-Dieter,DEX, Methods and systems for functionally describing a digital hardware design and for converting a functional specification of same into a netlist.
  22. Borrelli ; Ronald N., Programmable tester method and apparatus.
  23. Childs Philip Lee (Raleigh NC) Skovira Joseph Francis (Binghamton NY), Sets and holds in virtual time logic simulation for parallel processors.
  24. Noy Amos,ILX, System and method for applying flexible constraints.
  25. McNamara Michael Thomas York ; Tan Chong Guan ; Massey David Todd, System and method for automated design verification.
  26. Valind Thomas S. (New Brighton MN), System and method for satisfying mutually exclusive gating requirements in automatic test pattern generation systems.
  27. Aharon Aharon,ILX ; Malka Yossi,ILX ; Lichtenstein Yossi,ILX, Test program generator.
  28. Langhof Marco (Magdeburg DEX) Biwer Alfred (Ammerbuch DEX), Testing apparatus for testing and handling a multiplicity of devices.
  29. Kasuya Atsushi, Verification system for circuit simulator.
  30. Kasuya Atsushi, Verification system for simulator.

이 특허를 인용한 특허 (16)

  1. VanGilder, James William; Healey, Christopher M.; Zhang, Xuanhang, Analysis of effect of transient events on temperature in a data center.
  2. Cook,Stephen; Broadley,Simon; Bilton,Mark; Farr,Mark; Wimpory,Ben; Hewitt,Lee; Glover,Tim, Apparatus and method for managing integrated circuit designs.
  3. Primm,Michael; Jefts, Jr.,Richard, Extensible sensor monitoring, alert processing and notification system and method.
  4. Faulkner, Gary; Martinek, Joshua Thomas, Method and apparatus for collecting and displaying network device information.
  5. Faulkner, Gary; Martinek, Joshua Thomas, Method and apparatus for collecting and displaying network device information.
  6. Childers, Sloan; Moran, Mike; Elderton, John; Medford, Mitch, Method and apparatus for replay of historical data.
  7. Primm, Michael; Fowler, John J.; Faulkner, Gary, Method and system for a set of network appliances which can be connected to provide enhanced collaboration, scalability, and reliability.
  8. Primm, Michael, Method and system for journaling and accessing sensor and configuration data.
  9. Primm, Michael, Method and system for journaling and accessing sensor and configuration data.
  10. Fowler, John J.; Cullen, Gerard L., Method and system for monitoring computer networks and equipment.
  11. Fowler, John J.; Cullen, Gerard L., Method and system for monitoring computer networks and equipment.
  12. Fowler, John J.; Cullen, Gerard L., Method and system for monitoring computer networks and equipment.
  13. Childers, Sloan K.; Elderton, John; Primm, Michael, Methods for displaying physical network topology and environmental status by location, organization, or responsible party.
  14. Childers, Sloan K.; Elderton, John; Primm, Michael, Methods for displaying physical network topology and environmental status by location, organization, or responsible party.
  15. Krishna Mohan, Srivathsan; Xu, Youming, Sequential logic sensitization from structural description.
  16. White, Sean, Systems and methods for journaling and executing device control instructions.
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