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Multiple loadlock system 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/00
  • B65H-005/00
출원번호 US-0429175 (1999-10-28)
발명자 / 주소
  • Roger V. Heyder
  • Thomas B. Brezocsky
  • Robert E. Davenport
출원인 / 주소
  • Applied Materials, Inc.
대리인 / 주소
    Konrad, Raynes, Victor & Mann
인용정보 피인용 횟수 : 33  인용 특허 : 48

초록

A semiconductor processing system having a holding chamber coupled to a mainframe processing system and at least one loadlock chamber coupled to the holding chamber in which unprocessed wafers are transferred from the loadlock chamber to the holding chamber for subsequent processing by the mainframe

대표청구항

1. A semiconductor workpiece processing system, comprising:a mainframe chamber having at least one pair of adjacent processing chambers coupled to said mainframe chamber; a pressure-tight holding chamber coupled to said mainframe chamber; a first pressure-tight cassette chamber having a first casset

이 특허에 인용된 특허 (48)

  1. Kato Susumu,JPX ; Ozawa Masahito,JPX ; Muraoka Sunao,JPX, Apparatus and method for regulating pressure in two chambers.
  2. Hazano Shigeki (Yokohama CA JPX) Shibagaki Masahiro (San Jose CA) Jyo Hidetaka (Sagamihara JPX) Sensui Reiichiro (Sagamihara JPX) Iwami Munenori (Yokohama JPX) Suzuki Noboru (Chigasaki JPX), Apparatus for producing semiconductor devices.
  3. Hofmeister Christopher A. ; Kiley Christopher C., Batch loader arm.
  4. Beaver ; II Robert I. (Menlo Park CA) Adams Michael J. (San Jose CA) Prodanovich George L. (Campbell CA) Key Paul F. (San Martin CA) Rawlings Don O. (San Jose CA) Santhanam P. (Sunnyvale CA) Hunt Sus, Buffer storage apparatus for semiconductor wafer processing.
  5. Crabb Richard (Mesa AZ) Robinson McDonald (Paradise Valley AZ) Hawkins Mark R. (Mesa AZ) Goodwin Dennis L. (Tempe AZ) Ferro Armand P. (Scottsdale AZ) Ozias Albert E. (Aumsville OR) deBoer Wiebe B. (E, Chemical vapor deposition system.
  6. Ishii Katsumi (Fujino JPX) Asano Takanobu (Yokohama JPX) Abe Masaharu (Sagamihara JPX) Yamaga Kenichi (Sagamihara JPX) Sakata Kazunari (Sagamihara JPX) Tanahashi Takashi (Machida JPX) Moriya Syuji (Y, Clean air apparatus.
  7. Shiraiwa Hirotsugu (Hino JPX), Conveyor apparatus.
  8. Nogami Mamoru (Uji JPX), End station for an ion implantation apparatus.
  9. Devilbiss John J. (San Mateo CA) Glaze James A. (Danville CA) Lugosi Steve (Fremont CA) McNaughton Allen D. (Fremont CA) Ozaraki Robert G. (Livermore CA), Enhanced vertical thermal reactor system.
  10. Shidahara Hitoshi (Okayama JPX) Yamamoto Syozi (Ibara JPX), Equipment for heating and cooling substrates for coating photo resist thereto.
  11. Yokoyama Natsuki,JPX ; Kawamoto Yoshifumi,JPX ; Murakami Eiichi,JPX ; Uchida Fumihiko,JPX ; Mizuishi Kenichi,JPX ; Kawamura Yoshio,JPX, Fabrication system and method having inter-apparatus transporter.
  12. Tepman Avi, Front end vacuum processing environment.
  13. Altwood Allen ; Colborne Kelly ; Fairbairn Kevin ; Lane Christopher ; Ponnekanti Hari K. ; Sundar Satish, Front end wafer staging with wafer cassette turntables and on-the-fly wafer center finding.
  14. Ohsawa Tetsu (Sagamihara JPX), Heat treating apparatus.
  15. Zajac John (San Jose CA) Mirkovich Ninko T. (Novato CA) Rathmann Thomas M. (Rohnert Park CA) Lachenbruch Roger B. (Petaluma CA), Modular article processing machine and method of article handling therein.
  16. Maydan Dan (Los Altos Hills CA) Somekh Sasson (Redwood City CA) Wang David N. (Cupertino CA) Cheng David (San Jose CA) Toshima Masato (San Jose CA) Harari Isaac (Mountain View CA) Hoppe Peter D. (Sun, Multi-chamber integrated process system.
  17. Ozawa Masahito (Yamanashi JPX) Mizukami Masami (Yamanashi JPX) Kanazashi Masanobu (Kofu JPX) Takasoe Toshihiko (Yamanashi JPX) Narushima Masaki (Yamanashi JPX) Kubodera Masao (Yamanashi JPX), Multi-chamber system provided with carrier units.
  18. Asakawa Teruo,JPX ; Saeki Hiroaki,JPX, Multi-chamber treatment system.
  19. Maydan Dan (Los Altos Hills CA) Somekh Sasson (Redwood City CA) Wang David N. (Cupertino CA) Cheng David (San Jose CA) Toshima Masato (San Jose CA) Harari Isaac (Mountain View CA) Hoppe Peter D. (Sun, Multichamber integrated process system.
  20. Maydan Dan ; Somekh Sasson ; Wang David Nin-Kou ; Cheng David ; Toshima Masato ; Harari Isaac ; Hoppe Peter D., Multiple chamber integrated process system.
  21. Saiki Kazuyoshi (Yamanashi JPX), Reduced-pressure processing apparatus.
  22. Krueger Gordon P. (San Jose CA), Reducing particulates during semiconductor fabrication.
  23. Tateyama Kiyohisa (Kumamoto) Akimoto Masami (Kumamoto) Ushijima Mitsuru (Tama JPX), Resist process system.
  24. Grunes Howard (Santa Cruz CA) Tepman Avi (Cupertino CA) Lowrance Robert (Los Gatos CA), Robot assembly.
  25. Bramhall ; Jr. Robert B. (Gloucester MA) Cloutier Richard M. (Salisbury MA) Laber Albert P. (Revere MA) Muka Richard S. (Topsfield MA), Sealing apparatus for a vacuum processing system.
  26. Tepman Avi (Cupertino CA) Grunes Howard (Santa Cruz CA) Somekh Sasson (Los Altos Hills CA) Maydan Dan (Los Altos Hills CA), Staged-vacuum wafer processing system and method.
  27. Harada Junji (Kumamoto JPX) Harada Ichiro (Kumamoto JPX) Nakamura Koji (Kumamoto JPX), Substrate processing method and substrate processing apparatus.
  28. Akimoto Masami,JPX, Substrate processing system.
  29. Yonemitsu Shuji,JPX ; Karino Toshikazu,JPX ; Yoshida Hisashi,JPX ; Watahiki Shinichiro,JPX ; Yoshida Yuji,JPX ; Shimura Hideo,JPX ; Sugimoto Takeshi,JPX ; Aburatani Yukinori,JPX ; Ikeda Kazuhito,JPX, Substrate transferring mechanism.
  30. Muka Richard S. ; Davis ; Jr. James C. ; Hofmeister Christopher A., Substrate transport apparatus with double substrate holders.
  31. Hofmeister Christopher A., Swap out plate and assembly.
  32. Lowrance Robert B. (Los Gatos CA), Two-axis magnetically coupled robot.
  33. Wagner Rudolf (Fontnas CHX) Martin Bader (Balzers LIX) Eberhard Moll (Schellenberg LIX) Zanardo Renzo (Balzers LIX) Van Agtmaal J. G. (Hilversum NLX), Vacuum apparatus.
  34. Toshima Masato (Campbell CA), Vacuum chamber slit valve.
  35. Fukasawa Yoshio (Kofu JPX) Hosoda Shozo (Yamanashi-ken JPX) Nakagome Tatsuya (Yamanashi-ken JPX) Tozawa Takashi (Yamanashi-ken JPX) Suzuki Koji (Yamanashi-ken JPX) Ishihara Yasumasa (Kofu JPX) Aoyagi, Vacuum process apparatus and vacuum processing method.
  36. Soraoka Minoru,JPX ; Yoshioka Ken,JPX ; Kawasaki Yoshinao,JPX, Vacuum processing apparatus and semiconductor manufacturing line using the same.
  37. Kato Shigekazu,JPX ; Nishihata Kouji,JPX ; Tsubone Tsunehiko,JPX ; Itou Atsushi,JPX, Vacuum processing apparatus for substate wafers.
  38. Kato Shigekazu (Kudamatsu JPX) Tamura Naoyuki (Kudamatsu JPX) Nishihata Kouji (Tokuyama JPX) Tsubone Tsunehiko (Hikari JPX) Itou Atsushi (Kudamatsu JPX), Vacuum processing system.
  39. Kato Shigekazu (Kudamatsu JPX) Tamura Naoyuki (Kudamatsu JPX) Nishihata Kouji (Tokuyama JPX) Tsubone Tsunehiko (Hikari JPX) Itou Atsushi (Kudamatsu JPX) Nakata Kenji (Hikari JPX) Ogawa Yoshifumi (Hik, Vacuum processing system.
  40. Otwell Robert ; Nering Eric A. ; Lossberg Bryan Von, Wafer aligner in center of front end frame of vacuum system.
  41. Murata Masanao (Ise JPX) Yamashita Teppei (Ise JPX) Tanaka Tsuyoshi (Ise JPX) Hoshiko Takahide (Ise JPX) Karita Mitsuji (Ise JPX) Kawano Hitoshi (Ise JPX) Shinya Tutomu (Ise JPX), Wafer conveying system in a clean room.
  42. Chrisos John M. (Beverly MA) Fowler ; Jr. Bertram F. (Danvers MA) Muka Richard S. (Topsfield MA), Wafer handling apparatus.
  43. Iwabuchi Katsuhiko (Sagamihara JPX) Takanabe Eiichirou (Kanagawa-Ken JPX), Wafer processing apparatus.
  44. Hertel Richard J. (Bradford MA) Delforge Adrian C. (Rockport MA) Mears Eric L. (Rockport MA) MacIntosh Edward D. (Gloucester MA) Jennings Robert E. (Nethuen MA) Bhargava Akhil (Reading MA), Wafer transfer system.
  45. Toshima Masato, Wafer transfer system and method of using the same.
  46. Wiesler Mordechai (Lexington MA) Weiss Mitchell (Haverford PA), Wafer transfer system having rotational capability.
  47. Somekh Sasson (Los Altos Hills CA) Fairbairn Kevin (Saratoga CA) Kolstoe Gary M. (Fremont CA) White Gregory W. (San Carlos CA) Faraco ; Jr. W. George (Saratoga CA), Wafer tray and ceramic blade for semiconductor processing apparatus.
  48. Somekh Sasson (Los Altos Hills CA) Fairbairn Kevin (Saratoga CA) Kolstoe Gary M. (Fremont CA) White Gregory W. (San Carlos CA) Faraco ; Jr. W. George (Saratoga CA), Wafer tray and ceramic blade for semiconductor processing apparatus.

이 특허를 인용한 특허 (33)

  1. Lee,Jae Chull; Berkstresser,David, Curved slit valve door with flexible coupling.
  2. Lee, Jae-Chull; Kurita, Shinichi; White, John M.; Anwar, Suhail, Decoupled chamber body.
  3. Kurita, Shinichi; Blonigan, Wendell T., Double dual slot load lock chamber.
  4. Kurita, Shinichi; Blonigan, Wendell T.; Hosokawa, Akihiro, Dual substrate loadlock process equipment.
  5. Kurita, Shinichi; Blonigan, Wendell T.; Tanase, Yoshiaki, Large area substrate transferring method for aligning with horizontal actuation of lever arm.
  6. Meulen, Peter van der, Linear semiconductor processing facilities.
  7. van der Meulen, Peter, Linear semiconductor processing facilities.
  8. Kurita,Shinichi; Blonigan,Wendell T.; Tanase,Yoshiaki, Load lock chamber for large area substrate processing system.
  9. Kurita,Shinichi; Blonigan,Wendell T., Load lock chamber having two dual slot regions.
  10. Lee, Jae-Chull; Anwar, Suhail; Kurita, Shinichi, Load lock chamber with decoupled slit valve door seal compartment.
  11. Kurita,Shinichi; Blonigan,Wendell T., Method for transferring substrates in a load lock chamber.
  12. van der Meulen, Peter, Mid-entry load lock for semiconductor handling system.
  13. van der Meulen,Peter, Mid-entry load lock for semiconductor handling system.
  14. Kurita, Shinichi; Anwar, Suhail; Lee, Jae-Chull, Multiple slot load lock chamber and method of operation.
  15. van der Meulen, Peter, Semiconductor manufacturing systems.
  16. van der Meulen, Peter, Semiconductor manufacturing systems.
  17. van der Meulen, Peter, Semiconductor manufacturing systems.
  18. van der Meulen, Peter; Kiley, Christopher C; Pannese, Patrick D.; Ritter, Raymond S.; Schaefer, Thomas A., Semiconductor wafer handling and transport.
  19. van der Meulen, Peter; Kiley, Christopher C; Pannese, Patrick D.; Ritter, Raymond S.; Schaefer, Thomas A., Semiconductor wafer handling and transport.
  20. van der Meulen, Peter; Kiley, Christopher C.; Pannese, Patrick D.; Ritter, Raymond S.; Schaefer, Thomas A., Semiconductor wafer handling transport.
  21. van der Meulen, Peter, Stacked process modules for a semiconductor handling system.
  22. van der Meulen,Peter, Stacked process modules for a semiconductor handling system.
  23. Jo, Cheol Rae; Park, Jang-Wan; Jeong, Won Ki, Substrate processing apparatus.
  24. Enokida, Suguru; Nakaharada, Masahiro; Miyata, Akira; Kiyama, Hidekazu; Iida, Naruaki, Substrate processing apparatus, substrate processing method and storage medium.
  25. Wakabayashi, Shinji, Substrate processing system, substrate processing method and storage medium.
  26. Onodera, Shinobu; Numakura, Masahiro, Substrate receiving method and controller.
  27. Sakaue, Hiromitsu; Yamaguchi, Hirofumi, Substrate transfer apparatus and substrate transfer method.
  28. Kim, Dong Ho; Choi, Jinyoung; Go, Jaeseung; Hwang, Soomin, System and method for treating substrate.
  29. Tamai,Tadamoto, Vacuum processing system being able to carry process object into and out of vacuum chamber.
  30. Kim, Sam Hyungsam; Lee, Jae-Chull; Sterling, William N.; Brown, Paul, Valve door with ball coupling.
  31. Sieradzki,Manny; White,Nicholas R., Wafer handling apparatus and method.
  32. Chan, Soon Chye, Wafer handling system for a loadlock.
  33. Mitchell,Robert J.; Weed,Allan D.; Gueler,Richard, Work-piece treatment system having load lock and buffer.
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