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Method of forming copper interconnection utilizing aluminum capping film 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0411266 (1999-10-04)
발명자 / 주소
  • Stuart E. Greer
출원인 / 주소
  • Motorola, Inc.
대리인 / 주소
    Robert A. Rodriguez
인용정보 피인용 횟수 : 73  인용 특허 : 6

초록

A mostly copper-containing interconnect (126) overlies a semiconductor device substrate (100), and a transitional metallurgy structure (312, 508, 716, 806) that includes an aluminum-containing film (200, 506, 702, 802) contacts a portion of the mostly copper-containing interconnect. In one embodimen

대표청구항

1. A method for forming a semiconductor device, comprising:forming a first mostly copper-containing bond pad overlying a semiconductor device substrate; forming a chromium-containing adhesion film over the mostly copper-containing bond pad; forming an aluminum-containing capping film overlying the c

이 특허에 인용된 특허 (6)

  1. Brady Michael J. (Brewster NY) Kang Sung K. (Millwood NY) Moskowitz Paul A. (Yorktown Heights NY) Ryan James G. (Essex Junction VT) Reiley Timothy C. (Ridgefield CT) Walton Erick G. (Johnson VT) Bick, Aluminum bump, reworkable bump, and titanium nitride structure for tab bonding.
  2. Motsiff William Thomas ; Geffken Robert Michael ; Uttecht Ronald Robert, Integrated pad and fuse structure for planar copper metallurgy.
  3. Motsiff William Thomas ; Geffken Robert Michael ; Uttecht Ronald Robert, Integrated pad and fuse structure for planar copper metallurgy.
  4. Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Method of making contact tip structures.
  5. Costrini Gregory ; Goldblatt Ronald Dean ; Heidenreich ; III John Edward ; McDevitt Thomas Leddy, Method/structure for creating aluminum wirebound pad on copper BEOL.
  6. Edelstein Daniel Charles ; McGahay Vincent ; Nye ; III Henry A. ; Ottey Brian George Reid ; Price William H., Robust interconnect structure.

이 특허를 인용한 특허 (73)

  1. Wang, Chung Yu; Lee, Chien-Hsiun, Aluminum cap for reducing scratch and wire-bond bridging of bond pads.
  2. Kang, Seung H.; Krebs, Roland P.; Steiner, Kurt George; Ayukawa, Michael C.; Merchant, Sailesh Mansinh, Aluminum pad power bus and signal routing for integrated circuit devices utilizing copper technology interconnect structures.
  3. Yu, Chen-Hua; Tseng, Horng-Huei, Bonding structure and fabrication thereof.
  4. Huang,Min Lung, Bump electrodes having multiple under ball metallurgy (UBM) layers.
  5. Fan, Yang-Tung; Chu, Cheng-Yu; Fan, Fu-Jier; Lin, Shih-Jane; Peng, Chiou-Shian; Chen, Yen-Ming; Lin, Kuo-Wei, Bumping process to increase bump height and to create a more robust bump structure.
  6. Lee, Jin-Yuan; Lo, Hsin-Jung, Chip assembly with interconnection by metal bump.
  7. Lin, Mou-Shiung; Lee, Jin-Yuan, Chip packages having dual DMOS devices with power management integrated circuits.
  8. Arvin, Charles L.; Gambino, Jeffrey P.; Musante, Charles F.; Muzzy, Christopher D.; Sauter, Wolfgang, Corrosion resistant aluminum bond pad structure.
  9. Arvin, Charles L.; Gambino, Jeffrey P.; Musante, Charles F.; Muzzy, Christopher D.; Sauter, Wolfgang, Corrosion resistant aluminum bond pad structure.
  10. Eppes,David H., Crack resistant scribe line monitor structure and method for making the same.
  11. Thei, Kong-Beng; Cheng, Chung Long; Liu, Chung-Shi; Chuang, Harry-Hak-Lay; Wu, Shien-Yang; Chen, Shi-Bai, E-fuse structure design in electrical programmable redundancy for embedded memory circuit.
  12. Thei, Kong-Beng; Cheng, Chung Long; Liu, Chung-Shi; Chuang, Harry-Hak-Lay; Wu, Shien-Yang; Chen, Shi-Bai, E-fuse structure design in electrical programmable redundancy for embedded memory circuit.
  13. Farnworth, Warren M., Electronic device package structures.
  14. Wang, Pu; Shih, Ying-Ching; Lu, Szu-Wei; Lin, Jing-Cheng, Fan out package structure and methods of forming.
  15. Wang, Pu; Shih, Ying-Ching; Lu, Szu-Wei; Lin, Jing-Cheng, Fan out package structure and methods of forming.
  16. Yoon, Jung-Lim; Ahn, Jong-Hyon; Lee, Chang-Hun, Flip chip type semiconductor device and method of fabricating the same.
  17. Thei, Kong-Beng; Cheng, Chung Long; Liu, Chung-Shi; Chuang, Harry; Wu, Shien-Yang; Chen, Shi-Bai, Fuse structure.
  18. Boeck, Josef; Knapp, Herbert; Liebl, Wolfgang; Schaefer, Herbert, Fuse structure and method for manufacturing same.
  19. Adkisson, James W.; Maciejewski, Edward; Smeys, Peter; Stamper, Anthony K., Fuse structure with thermal and crack-stop protection.
  20. Lin, Mou-Shiung, High performance IC chip having discrete decoupling capacitors attached to its IC surface.
  21. Chou, Chiu-Ming; Lee, Jin-Yuan, Integrated circuit (IC) chip and method for fabricating the same.
  22. Lin, Mou-Shiung; Lee, Jin-Yuan, Integrated circuit and method for fabricating the same.
  23. Lin, Mou-Shiung; Lee, Jin-Yuan, Integrated circuit and method for fabricating the same.
  24. Minn, Eun-young; Park, Young-hoon; Lee, Chi-Hoon; Ban, Hyo-dong, Integrated circuit chip having anti-moisture-absorption film at edge thereof and method of forming anti-moisture-absorption film.
  25. Fischer, Armin; Von Glasow, Alexander, Integrated circuit with pads connected by an under-bump metallization and method for production thereof.
  26. Drexl, Stefan; Goebel, Thomas; Helneder, Johann; Hommel, Martina; Klein, Wolfgang; Kôrner, Heinrich; Mitchell, Andrea; Schwerd, Markus; Seck, Martin, Integrated connection arrangements.
  27. Tang, Sanh D.; Tuttle, Mark E.; Cook, Keith R., Interconnect structures with bond-pads and methods of forming bump sites on bond-pads.
  28. Tang,Sanh D.; Tuttle,Mark E.; Cook,Keith R., Interconnect structures with bond-pads and methods of forming bump sites on bond-pads.
  29. Gambino, Jeffrey P.; He, Zhong-Xiang; Lee, Tom C., Isolated wire structures with reduced stress, methods of manufacturing and design structures.
  30. Gambino, Jeffrey P.; He, Zhong-Xiang; Lee, Tom C., Isolated wire structures with reduced stress, methods of manufacturing and design structures.
  31. Kim,Su Hyun, Method for forming bond pad openings.
  32. Burrell,Lloyd G.; Davis,Charles R.; Goldblatt,Ronald D.; Landers,William F.; Mehta,Sanjay C., Method of fabricating a wire bond pad with Ni/Au metallization.
  33. Chen,Sheng Hsiung, Method of improving copper pad adhesion.
  34. Spencer, Gregory S.; Crabtree, Philip E.; Denning, Dean J.; Junker, Kurt H.; Martin, Gerald A., Method of making a die with recessed aluminum die pads.
  35. Spencer, Gregory S.; Crabtree, Phillip E.; Denning, Dean J.; Junker, Kurt H.; Martin, Gerald A., Method of making a die with recessed aluminum die pads.
  36. Momoto,Seiji; Mochizuki,Eiji, Method of manufacturing semiconductor device.
  37. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  38. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  39. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  40. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  41. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  42. Lee, Jin-Yuan; Chen, Ying-chih, Method of wire bonding over active area of a semiconductor circuit.
  43. Hill, Darrell G.; Bowles, Philip H.; Campbell, Jan; Daly, Terry K.; Fender, Jason R.; Ramanathan, Lakshmi N.; Tracht, Neil T., Microelectronic assembly with back side metallization and method for forming the same.
  44. Skala, Steven L; Bothra, Subhas; Demuizon, Emmanuel, Pad metallization over active circuitry.
  45. Wang,Tsing Chow, Planar bond pad design and method of making the same.
  46. Yap, Daniel; Lawyer, Philip H., Precision electroplated solder bumps and method for manufacturing thereof.
  47. Barth, Hans-Joachim; Burrell, Lloyd G.; Friese, Gerald R.; Stetter, Michael, Process for forming fusible links.
  48. Wang, Chien-Jung; Lin, Jian-Hong, Seal ring structures with reduced moisture-induced reliability degradation.
  49. Wang, Chien-Jung; Lin, Jian-Hong, Seal ring structures with reduced moisture-induced reliability degradation.
  50. Tsao,Pei Haw; Huang,Chender; Hou,Shang Yu; Su,Chao Yuan; Hsu,Chia Hsiung, Semiconductor bond pad structures and methods of manufacturing thereof.
  51. Lin, Mou-Shiung; Lee, Jin-Yuan, Semiconductor chip structure.
  52. Hatano,Keisuke; Abiru,Takahisa, Semiconductor device.
  53. Yamaya, Kazufumi; Shimomura, Koji, Semiconductor device and method for fabricating the same.
  54. Yamaya,Kazufumi; Shimomura,Koji, Semiconductor device and method for fabricating the same.
  55. Abiru, Takahisa; Hatano, Keisuke, Semiconductor device and method for manufacturing the same.
  56. Moriyama, Kei; Tamaki, Shuichi; Sako, Shuichi; Kori, Mitsuhide; Goto, Junji; Sawada, Tatsuya, Semiconductor device and method of manufacturing the same.
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  59. Song,Young Hee; Choi,Ill Heung; Son,Min Young; Park,Min Sang, Semiconductor device having fuse circuit on cell region and method of fabricating the same.
  60. Lindgren, Joseph T., Semiconductor device with copper wirebond sites and methods of making same.
  61. Lindgren, Joseph T., Semiconductor device with copper wirebond sites and methods of making same.
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  64. Lin, Yaojian; Zhang, Qing; Cao, Haijing, Semiconductor device with solder bump formed on high topography plated Cu pads.
  65. Coolbaugh, Douglas D.; Edelstein, Daniel C.; Eshun, Ebenezer E.; He, Zhong-Xiang; Rassel, Robert M.; Stamper, Anthony K., Terminal pad structures and methods of fabricating same.
  66. Coolbaugh,Douglas D.; Edelstein,Daniel C.; Eshun,Ebenezer E.; He,Zhong Xiang; Rassel,Robert M.; Stamper,Anthony K., Terminal pad structures and methods of fabricating same.
  67. Coolbaugh,Douglas D.; Edelstein,Daniel C.; Eshun,Ebenezer E.; He,Zhong Xiang; Rassel,Robert M.; Stamper,Anthony K., Terminal pad structures and methods of fabricating same.
  68. Daubenspeck, Timothy H.; Gambino, Jeffrey P.; Motsiff, William T., Thinning of fuse passivation after C4 formation.
  69. You, Lu; Wang, Fei; Ngo, Minh Van, Use of sic for preventing copper contamination of dielectric layer.
  70. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Very thick metal interconnection scheme in IC chips.
  71. Lin, Mou-Shiung; Wei, Gu-Yeon, Voltage regulator integrated with semiconductor chip.
  72. Lin, Mou-Shiung; Chen, Michael; Chou, Chien-Kang; Chou, Mark, Wirebond pad for semiconductor chip or wafer.
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