초록 ▼

The reliability, electromigration resistance, adhesion, and electrical contact resistance of planarized, in-laid metallization patterns, e.g., of copper, are enhanced by a process comprising selectively depositing on the planarized, upper surfaces of the metallization features at least one thin laye

The reliability, electromigration resistance, adhesion, and electrical contact resistance of planarized, in-laid metallization patterns, e.g., of copper, are enhanced by a process comprising selectively depositing on the planarized, upper surfaces of the metallization features at least one thin layer comprising at least one passivant element for the metal of the features, reacting the at least one passivant element to chemically reduce any deleterious oxide layer present at the upper surfaces of the metallization features, and diffusing the at least one passivant element for a distance below the upper surface to form a passivated top interface. The passivated top interfaces advantageously exhibit reduced electromigration and improved adhesion to overlying metallization with lower ohmic contact resistance. Planarization, as by CMP, may be performed subsequent to reaction/diffusion to remove any elevated, reacted and/or unreacted portions of the at least one thin layer. The invention finds particular utility in "back-end" metallization processing of high-density integrated circuit semiconductor devices having sub-micron dimensioned metallization features.

대표청구항 ▼

1. A method of manufacturing an electrical device, which method comprises the sequential steps of:(a) providing a substrate including at least one damascene-type, metal feature in-laid in the exposed, upper surface of a layer of dielectric material overlying at least a portion of said substrate, the

1. A method of manufacturing an electrical device, which method comprises the sequential steps of:(a) providing a substrate including at least one damascene-type, metal feature in-laid in the exposed, upper surface of a layer of dielectric material overlying at least a portion of said substrate, the at least one metal feature including an upper, exposed surface substantially co-planar with said upper surface of said layer of dielectric material; (b) selectively depositing only on said exposed upper surface of said at least one metal feature at least one layer comprising at least one metallic passivant element for passivating said upper surface of said at least one metal feature, said at least one metallic passivant element selected from the group consisting of magnesium (Mg), titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), palladium (Pd), and chromium (Cr); and (c) effecting reaction between at least a portion of said at least one layer comprising at least one metallic passivant element and said upper surface of said at least one metal feature to form a passivating layer thereat, whereby electromigration of the metal of said at least one metal feature is minimized or substantially prevented.