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Method for fabricating lateral PNP heterojunction bipolar transistor and related structure 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-031/0328
출원번호 US-0853735 (2001-05-10)
발명자 / 주소
  • Klaus F. Schuegraf
출원인 / 주소
  • Newport Fab
대리인 / 주소
    Farjami & Farjami LLP
인용정보 피인용 횟수 : 18  인용 특허 : 9

초록

According to one embodiment, a dielectric layer is deposited over an n-well. For example, the dielectric layer can be silicon dioxide, silicon nitride or a low-k dielectric. Subsequently, the dielectric layer is etched to fabricate an opening over the n-well. An interfacial oxide layer is next forme

대표청구항

1. A method for fabricating a lateral PNP transistor, said method comprising steps of:depositing a dielectric layer on a top surface of an n-well in a semiconductor substrate; etching said dielectric layer so as to fabricate an opening over said n-well, said top surface of said n-well being exposed

이 특허에 인용된 특허 (9)

  1. Mori Hideki,JPX ; Gomi Takayuki,JPX, Heterojunction bipolar semiconductor device.
  2. Yamazaki Toru (Tokyo JPX), Heterojunction bipolar transistor having particular Ge distributions and gradients.
  3. Morishita Masakazu,JPX, Heterojunction bipolar transistor structure.
  4. Kovacic Stephen J. (Kanata CAX), Lateral bipolar transistor.
  5. Cook Robert K. (Poughkeepsie) Knepper Ronald W. (Lagrangeville) Kulkarni Subodh K. (Fishkill) Lange Russell C. (Newburgh) Ronsheim Paul A. (Wappingers Falls) Subbanna Seshadri (Hopewell Junction) Tej, Method for controlling interfacial oxide at a polycrystalline/monocrystalline silicon interface.
  6. Ryum Byung-Ryul,KRX ; Han Tae-Hyeon,KRX ; Cho Deok-Ho,KRX ; Lee Soo-Min,KRX ; Pyun Kwang-Eui,KRX, Method for fabricating heterojunction bipolar transistor.
  7. Marty Michel,FRX ; Chantre Alain,FRX ; Schwartzmann Thierry,FRX, Method of selectively doping the intrinsic collector of a vertical bipolar transistor with epitaxial base.
  8. Bashir Rashid (Santa Clara CA) Hebert Francois (Sunnyvale CA), Self-aligned polysilicon base contact in a bipolar junction transistor.
  9. Inou Kazumi (Yokohama JPX) Katsumata Yasuhiro (Chigasaki JPX), Semiconductor device and manufacturing method thereof.

이 특허를 인용한 특허 (18)

  1. Enicks, Darwin Gene; Carver, Damian, Bandgap and recombination engineered emitter layers for SiGe HBT performance optimization.
  2. Enicks,Darwin Gene; Carver,Damian, Bandgap engineered mono-crystalline silicon cap layers for SiGe HBT performance enhancement.
  3. Enicks,Darwin Gene, Method and system for controlled oxygen incorporation in compound semiconductor films for device performance enhancement.
  4. Joshi, Pankaj N.; Schuegraf, Klaus F., Method for fabricating interfacial oxide in a transistor and related structure.
  5. U'Ren, Greg D.; Schuegraf, Klaus F., Method for integrating a metastable base into a high-performance HBT and related structure.
  6. Hayashi,Masahiro, Method for manufacturing semiconductor device.
  7. Haeusler,Alfred; Steinmann,Philipp; Balster,Scott; El Kareh,Badih, Method of fabricating an integrated silicon-germanium heterobipolar transistor and an integrated silicon-germanium heterobipolar transistor.
  8. Ko, Tin Myint; Lehtola, Philip John; Ozalas, Matthew Thomas; Ripley, David Steven; Shao, Hongxiao; Zampardi, Jr., Peter J., Power amplifier modules including bipolar transistor with grading and related systems, devices, and methods.
  9. Ko, Tin Myint; Lehtola, Philip John; Ozalas, Matthew Thomas; Ripley, David Steven; Shao, Hongxiao; Zampardi, Jr., Peter J., Power amplifier modules including bipolar transistor with grading and related systems, devices, and methods.
  10. Chen, Howard E.; Guo, Yifan; Hoang, Dinhphuoc Vu; Janani, Mehran; Ko, Tin Myint; Lehtola, Philip John; LoBianco, Anthony James; Modi, Hardik Bhupendra; Nguyen, Hoang Mong; Ozalas, Matthew Thomas; Petty-Weeks, Sandra Louise; Read, Matthew Sean; Riege, Jens Albrecht; Ripley, David Steven; Shao, Hongxiao; Shen, Hong; Sun, Weimin; Sun, Hsiang-Chih; Welch, Patrick Lawrence; Zampardi, Jr., Peter J.; Zhang, Guohao, Power amplifier modules including related systems, devices, and methods.
  11. Zampardi, Jr., Peter J.; Sun, Hsiang-Chih; Shen, Hong; Janani, Mehran; Riege, Jens Albrecht, Power amplifier modules including tantalum nitride terminated through wafer via and related systems, devices, and methods.
  12. Modi, Hardik Bhupendra; Petty-Weeks, Sandra Louise; Shao, Hongxiao; Sun, Weimin; Zampardi, Jr., Peter J.; Zhang, Guohao, Power amplifier modules including wire bond pad and related systems, devices, and methods.
  13. Hoang, Dinhphuoc Vu; Modi, Hardik Bhupendra; Sun, Hsiang-Chih; Zampardi, Jr., Peter J.; Zhang, Guohao, Power amplifier modules with bifet and harmonic termination and related systems, devices, and methods.
  14. Modi, Hardik Bhupendra; Petty-Weeks, Sandra Louise; Shao, Hongxiao; Sun, Weimin; Zampardi, Jr., Peter J.; Zhang, Guohao, Power amplifier modules with bonding pads and related systems, devices, and methods.
  15. Sun, Weimin; Zampardi, Jr., Peter J.; Shao, Hongxiao; Zhang, Guohao; Modi, Hardik Bhupendra; Hoang, Dinhphuoc Vu, Power amplifier modules with harmonic termination circuit and related systems, devices, and methods.
  16. Zampardi, Jr., Peter J.; Sun, Hsiang-Chih; Petty-Weeks, Sandra Louise; Zhang, Guohao; Modi, Hardik Bhupendra, Power amplifier modules with power amplifier and transmission line and related systems, devices, and methods.
  17. Ripley, David Steven; Lehtola, Philip John; Zampardi, Jr., Peter J.; Shao, Hongxiao; Ko, Tin Myint; Ozalas, Matthew Thomas, Process-compensated HBT power amplifier bias circuits and methods.
  18. Ripley, David Steven; Lehtola, Philip John; Zampardi, Jr., Peter J.; Shao, Hongxiao; Ko, Tin Myint; Ozalas, Matthew Thomas, Process-compensated HBT power amplifier bias circuits and methods.
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