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Monolithic integrated circuit incorporating an inductive component and process for fabricating such an integrated circuit 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/00
출원번호 US-0525840 (2000-03-15)
우선권정보 FR-0003762 (1999-03-23)
발명자 / 주소
  • Laurent Basteres FR
  • Ahmed Mhani FR
  • Fran.cedilla.ois Valentin FR
  • Jean-Michel Karam FR
출원인 / 주소
  • Memscap S.A. FR
대리인 / 주소
    Wall Marjama & Bilinski LLP
인용정보 피인용 횟수 : 95  인용 특허 : 6

초록 ▼

A monolithic integrated circuit (1) incorporating an inductive component (2) and comprising:a semiconductor substrate layer (2);a passivation layer (4) covering the substrate layer (2);metal contact pads (5) connected to the substrate (2) and passing through the passivation layer (4) in order to be

대표청구항 ▼

1. A monolithic integrated circuit (1) incorporating an inductive component and comprising:a semiconductor substrate layer (2); a passivation layer (4) covering the substrate layer (2); metal contact pads (5) connected to the substrate (2) and passing through the passivation layer (4) in order to be

이 특허에 인용된 특허 (6)

  1. Ewen John E. (Yorktown Heights NY) Ponnapalli Saila (Fishkill NY) Soyuer Mehmet (Yorktown Heights NY), High-Q inductors in silicon technology without expensive metalization.
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  2. Kanehachi Kaoru (Tokyo JPX), Method of making a combined semiconductor device and inductor.
    상세보기
  3. Dow Stephen (Chandler AZ) Maass Eric C. (Scottsdale AZ) Marlin Bill (Phoenix AZ), Method of making an electronic device having an integrated inductor.
    상세보기
  4. Bhagat Jayant K. (930 Andover Way Los Altos CA 94022), Miniature inductor for integrated circuits and devices.
    상세보기
  5. Uemura Kazuyoshi,JPX ; Takahashi Kiyoshi,JPX, Planar-type inductor and fabrication method thereof.
    상세보기
  6. Imai Kiyotaka,JPX, Semiconductor device having spiral wiring directly covered with an insulating layer containing ferromagnetic particles.
    상세보기

이 특허를 인용한 특허 (95)

  1. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip package with die and substrate.
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  2. Lin, Mou-Shiung; Lee, Jin-Yuan, Chip packages having dual DMOS devices with power management integrated circuits.
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  3. Lin, Mou-Shiung, Chip structure with a passive device and method for forming the same.
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  4. Kuo, Nick; Chou, Chiu-Ming; Chou, Chien-Kang; Lin, Chu-Fu, Chip structure with bumps and testing pads.
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  5. Lin,Mou Shiung, Chip structure with redistribution traces.
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  6. Lin, Mou-Shiung, High performance system-on-chip discrete components using post passivation process.
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  7. Lin, Mou-Shiung, High performance system-on-chip discrete components using post passivation process.
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  8. Lin, Mou-Shiung, High performance system-on-chip discrete components using post passivation process.
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  9. Lin, Mou-Shiung, High performance system-on-chip inductor using post passivation process.
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  10. Lin, Mou Shiung, High performance system-on-chip passive device using post passivation process.
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  11. Lin, Mou-Shing, High performance system-on-chip using post passivation process.
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  13. Lin,Mou Shiung, High performance system-on-chip using post passivation process.
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  14. Lin,Mou Shiung, High performance system-on-chip using post passivation process.
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  15. Lee, Jin-Yaun; Lin, Mou-Shiung; Huang, Ching-Cheng, Integrated chip package structure using ceramic substrate and method of manufacturing the same.
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  16. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Integrated chip package structure using organic substrate and method of manufacturing the same.
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  17. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Integrated chip package structure using silicon substrate and method of manufacturing the same.
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  18. Ahn, Kie Y.; Forbes, Leonard, Integrated circuit inductors.
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  28. Hung,Cheng Chou; Tseng,Hua Chou; Liang,Victor Chiang; Chen,Yu Chia; Hsu,Tsun Lai, Method for fabricating a transformer integrated with a semiconductor structure.
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  29. Hung,Cheng Chou; Tseng,Hua Chou; Liang,Victor Chiang; Chen,Yu Chia; Hsu,Tsun Lai, Method for fabricating a transformer integrated with a semiconductor structure.
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  30. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Method for fabricating chip package with die and substrate.
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  31. Lin, Mou-Shiung; Lee, Jin-Yuan, Method for making high-performance RF integrated circuits.
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  32. Lin, Mou-Shiung; Lee, Jin-Yuan, Method for making high-performance RF integrated circuits.
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  33. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection process and structures.
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  35. Lin, Mou Shiung; Lee, Jin Yuan, Post passivation interconnection schemes on top of IC chip.
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  36. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
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  37. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
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  38. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
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  39. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
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  40. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
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  41. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
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  42. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
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  43. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
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  44. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
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  45. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
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  46. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
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  47. Lin, Mou Shiung; Lee, Jin Yuan, Post passivation interconnection schemes on top of IC chips.
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  48. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chips.
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  49. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chips.
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  50. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chips.
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  51. Lin, Mou-Shiung, Post passivation interconnection schemes on top of the IC chips.
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  52. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
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  53. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
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  57. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Post passivation interconnection schemes on top of the IC chips.
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  58. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
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  59. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
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  61. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
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  62. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
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  63. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection structures.
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  64. Lin, Mou-Shiung; Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng, Post passivation metal scheme for high-performance integrated circuit devices.
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  65. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation method for semiconductor chip or wafer.
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  68. Lee, Wen-Chieh; Lin, Mou-Shiung; Chou, Chien-Kang; Liu, Yi-Cheng; Chou, Chiu-Ming; Lee, Jin-Yuan, Semiconductor chip with coil element over passivation layer.
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  69. Lee, Wen-Chieh; Lin, Mou-Shiung; Chou, Chien-Kang; Liu, Yi-Cheng; Chou, Chiu-Ming; Lee, Jin-Yuan, Semiconductor chip with coil element over passivation layer.
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  70. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Semiconductor package with interconnect layers.
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