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Chip-scale semiconductor package of the fan-out type and method of manufacturing such packages 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/02
출원번호 US-0422027 (1999-10-20)
우선권정보 KR-0046564 (1998-10-31); KR-0046567 (1998-10-31); KR-0046569 (1998-10-31); KR-0046571 (1998-10-31); KR-0046574 (1998-10-31)
발명자 / 주소
  • Il Kwon Shim
  • Chang Kyu Park KR
  • Byung Joon Han KR
  • Vincent DiCaprio
  • Paul Hoffman
출원인 / 주소
  • Amkor Technology, Inc.
인용정보 피인용 횟수 : 75  인용 특허 : 28

초록

Chip-scale semiconductor packages of the fan-out type and methods of manufacturing such packages are disclosed. In one package embodiment within the invention, the package substrate is stiff enough to effectively carry an increased number of solder balls on an exterior area outside the edge of a sem

대표청구항

1. A semiconductor package comprising:a semiconductor chip having a first surface and a plurality of conductive pads on the first surface; a substrate having a first surface and an opposite second surface having a plurality of conductive metallizations thereon, wherein the chip is mounted on the fir

이 특허에 인용된 특허 (28)

  1. Schueller Randolph Dennis ; Geissinger John David, Chip scale ball grid array for integrated circuit package.
  2. Schueller Randolph D., Chip scale ball grid array for integrated circuit packaging.
  3. Lee Sang Hyuk (Suwon KRX), Chip-sized package having metal circuit substrate.
  4. Masukawa Fuminori,JPX, Electronic device assembly.
  5. Shen Ming-Tung (No. 60 ; Lane 328 ; Li-Shan St. Nei-Hu Dist. ; Taipei City TWX), Integrated circuit chip including superimposed upper and lower printed circuit boards.
  6. Parker Robert H. (Oakton VA) Pommer Richard J. (Canyon CA), Integrated circuit component package with integral passive component.
  7. Call Anson J. (Holmes NY) Meisner Stephen H. (Hudson NY) Pompeo Frank L. (Walden NY) Zitz Jeffrey A. (Poughkeepsie NY), Method for directly joining a chip to a heat sink.
  8. Djennas Frank (Austin TX) Nomi Victor K. (Round Rock TX) Pastore John R. (Leander TX) Reeves Twila J. (Austin TX) Postlethwait Les (Lexington TX), Method for making semiconductor device having no die supporting surface.
  9. Yoshihara Shinji,JPX ; Inomata Sumitomo,JPX ; Ohara Fumio,JPX ; Kurahashi Takashi,JPX, Method for manufacturing a semiconductor device.
  10. Jakowetz Wolf,DEX ; Fischer Helmut,DEX, Method for producing a plurality of semiconductor components.
  11. Smith John W. ; Fjelstad Joseph, Method of assembling a semiconductor chip package.
  12. Yang Te-Sheng,TWX ; Ho Kai-Kuang,TWX, Method of fabricating wafer-level package.
  13. Razon Eli ; Von Seggern Walter, Method of forming a chip scale package, and a tool used in forming the chip scale package.
  14. Sweis Jason (Sunnyvale CA) Gilleo Kenneth B. (West Kingston RI), Method of forming interface between die and chip carrier.
  15. Andros Frank E. (Binghamton NY) Bupp James R. (Endwell NY) DiPietro Michael (Vestal NY) Hammer Richard B. (Apalachin NY), Method of making an electronic package with a thermally conductive support member having a thin circuitized substrate an.
  16. Dando Ross S., Method of processing semiconductive material wafers and method of forming flip chips and semiconductor chips.
  17. Ishikura Takuro (Nara JPX), Method of producing magnetosensitive semiconductor devices.
  18. Hoffman Paul, Microelectronic device package having a heat sink structure for increasing the thermal conductivity of the package.
  19. Mitchell Craig ; Distefano Thomas H., Microelectronic encapsulation methods and equipment.
  20. Maynard Ronald S., Selectively activated shape memory device.
  21. Khandros Igor Y. (Peekskill NY) DiStefano Thomas H. (Bronxville NY), Semiconductor chip assemblies with fan-in leads.
  22. Khandros Igor Y. (Peekskill NY) DiStefano Thomas H. (Bronxville NY), Semiconductor chip assemblies with fan-in leads.
  23. Lee Kyu Jin,KRX ; Choi Wan Gyun,KRX, Semiconductor chip package using flexible circuit board with central opening.
  24. DiStefano Thomas H. (Bronxville NY) Grube Gary W. (Monroe NY) Khandros Igor Y. (Peekskill NY) Mathiew Gatan (Carmel NY), Semiconductor connection components and methods with releasable lead support.
  25. Yoshikazu Takahashi,JPX, Semiconductor device and method of manufacturing the same.
  26. Amagai Masazumi,JPX, Semiconductor device package.
  27. Heo Young Wook,KRX ; Han Byung Joon,KRX, Semiconductor package and method for fabricating the same.
  28. McMillan John R. (Southlake TX) Maslakow William H. (Lewisville TX) Castro Abram M. (Fort Worth TX), Thermally enhanced chip carrier package.

이 특허를 인용한 특허 (75)

  1. Zhao,Sam Ziqun; Khan,Reza ur Rahman, Apparatus and method for thermal and electromagnetic interference (EMI) shielding enhancement in die-up array packages.
  2. Zhao, Sam Ziqun; Khan, Reza-ur Rahman, Ball grid array package enhanced with a thermal and electrical connector.
  3. Zhao, Sam Ziqun; Khan, Reza-ur Rahman, Ball grid array package enhanced with a thermal and electrical connector.
  4. Zhao,Sam Ziqun; Khan,Reza ur Rahman, Ball grid array package enhanced with a thermal and electrical connector.
  5. Zhao,Sam Ziqun; Khan,Rezaur Rahman, Ball grid array package enhanced with a thermal and electrical connector.
  6. Khan, Reza-ur Rahman; Zhao, Sam Ziqun, Ball grid array package fabrication with IC die support structures.
  7. Zhao, Sam Ziqun; Khan, Rezaur Rahman; Law, Edward; Papageorge, Marc, Ball grid array package having one or more stiffeners.
  8. Khan, Reza-ur Rahman; Zhong, Chong Hua, Ball grid array package substrates and method of making the same.
  9. Khan,Reza ur Rahman; Zhong,Chong Hua, Ball grid array package substrates with a modified central opening and method for making the same.
  10. Zhao, Sam Ziqun; Khan, Reza-ur Rahman, Ball grid array package with patterned stiffener layer.
  11. Zhao, Sam Ziqun; Khan, Reza ur Rahman; Law, Edward; Papageorge, Marc, Ball grid array package with patterned stiffener surface and method of assembling the same.
  12. Zhao, Sam Ziqun; Rahman Khan, Reza ur, Ball grid array package with separated stiffener layer.
  13. Khan,Reza ur Rahman; Zhao,Sam Ziqun, Ball grid array package with stepped stiffener layer.
  14. Huang, Chien Ping; Lo, Randy H. Y., Ball grid array semiconductor package with exposed base layer.
  15. Morrison,Michael W., Ball grid array structures and tape-based method of manufacturing same.
  16. Morrison, Michael W., Ball grid array structures having tape-based circuitry.
  17. Morrison,Michael W., Ball grid array structures having tape-based circuitry.
  18. Khan, Reza-ur Rahman; Zhao, Sam Ziqun, Die down ball grid array package.
  19. Khan, Reza-Ur Rahman; Zhao, Sam Ziqun, Die down ball grid array packages and method for making same.
  20. Khan, Reza-ur Rahman; Zhao, Sam Ziqun, Die-down ball grid array package with die-attached heat spreader and method for making the same.
  21. Zhang,Tonglong; Khan,Reza ur Rahman, Die-up ball grid array package including a substrate capable of mounting an integrated circuit die and method for making the same.
  22. Zhang,Tonglong; Khan,Reza ur Rahman, Die-up ball grid array package with a heat spreader and method for making the same.
  23. Khan,Reza ur R; Zhao,Sam Z; Bacher,Brent, Die-up ball grid array package with attached stiffener ring.
  24. Zhao, Sam Z; Khan, Reza-ur R, Die-up ball grid array package with die-attached heat spreader.
  25. Zhao,Sam Ziqun; Khan,Reza ur Rahman, Die-up ball grid array package with enhanced stiffener.
  26. Khan,Reza ur Rahman; Zhao,Sam Ziqun; Bacher,Brent, Die-up ball grid array package with patterned stiffener opening.
  27. Khan,Reza ur R; Zhao,Sam Z; Bacher,Brent, Die-up ball grid array package with printed circuit board attachable heat spreader.
  28. Zhao,Sam Z; Khan,Reza ur R, Die-up ball grid array package with printed circuit board attachable heat spreader.
  29. Rahman Khan,Reza ur; Zhao,Sam Ziqun, Enhanced die-down ball grid array and method for making the same.
  30. Zhao,Sam Ziqun; Khan,Reza ur Rahman, Enhanced die-up ball grid array packages and method for making the same.
  31. Voegerl, Andreas; Liebl, Tilo; Bauer, Gerhard; Gebhardt, Marion; Wenk, Alexander; Wieczorek, Matthias; Henniger, Juergen; Baumann, Karl-Heinz, Flexible printed board.
  32. Pendse, Rajendra D., Flip chip interconnection pad layout.
  33. Pendse, Rajendra D., Flip chip interconnection pad layout.
  34. Pendse,Rajendra D., Flip chip interconnection pad layout.
  35. Pendse,Rajendra D., Flip chip interconnection pad layout.
  36. Corisis, David J.; Jiang, Tongbi, Flip chip with interposer.
  37. Corisis, David J.; Jiang, Tongbi, Flip chip with interposer, and methods of making same.
  38. Khan,Reza ur Rahman; Zhao,Sam Ziqun, IC die support structures for ball grid array package fabrication.
  39. Zhang, Tonglong, Integrated circuit device package having both wire bond and flip-chip interconnections and method of making the same.
  40. Zhang,Tonglong, Integrated circuit device package having both wire bond and flip-chip interconnections and method of making the same.
  41. Hu, Kunzhong; Cheah, Chuan, Interdigitated conductive support for GaN semiconductor die.
  42. Yee, Pak Hong; Lee, Teck Kheng, Intrinsic thermal enhancement for FBGA package.
  43. Yee,Pak Hong; Lee,Teck Kheng, Intrinsic thermal enhancement for FBGA package.
  44. Yee,Pak Hong; Lee,Teck Kheng, Intrinsic thermal enhancement for FBGA package.
  45. Zhong, Chong Hua; Khan, Rezaur Rahman, Low voltage drop and high thermal performance ball grid array package.
  46. Zhong, Chonghua; Khan, Reza-ur Rahman, Low voltage drop and high thermal performance ball grid array package.
  47. Zhong,Chong Hua; Rahman Khan,Reza ur, Low voltage drop and high thermal performance ball grid array package.
  48. Khan, Rezaur Rahman; Zhao, Sam Ziqun, Method and apparatus for cooling semiconductor device hot blocks and large scale integrated circuit (IC) using integrated interposer for IC packages.
  49. Zhao,Sam Ziqun; Khan,Reza ur Rahman, Method for assembling a ball grid array package with multiple interposers.
  50. Zhao,Sam Zinqun; Khan,Reza ur Rahman; Chaudhry,Imtiaz, Method for assembling a ball grid array package with two substrates.
  51. Moxham,Stephen F., Method for fabricating semiconductor component with stiffener and circuit decal.
  52. Zhao, Sam Ziqun; Khan, Reza-ur Rahman; Chaudhry, Imtiaz, Method for making an enhanced die-up ball grid array package with two substrates.
  53. Zhao,Sam Ziqun; Khan,Rezaur Rahman, Method of assembling a ball grid array package with patterned stiffener layer.
  54. Zhao, Sam Ziqun; Khan, Rezaur Rahman, Methods of making a die-up ball grid array package with printed circuit board attachable heat spreader.
  55. Fee, Setho Sing, Microelectronic devices having intermediate contacts for connection to interposer substrates, and associated methods of packaging microelectronic devices with intermediate contacts.
  56. Fee, Setho Sing, Microelectronic devices having intermediate contacts for connection to interposer substrates, and associated methods of packaging microelectronic devices with intermediate contacts.
  57. Zhao, Sam Ziqun; Khan, Reza-ur Rahman, Multipiece apparatus for thermal and electromagnetic interference (EMI) shielding enhancement in die-up array packages and method of making the same.
  58. Zhao,Sam Ziqun; Khan,Reza ur Rahman, Multipiece apparatus for thermal and electromagnetic interference (EMI) shielding enhancement in die-up array packages and method of making the same.
  59. Zhao, Sam Ziqun; Khan, Rezaur Rahman, No-lead IC packages having integrated heat spreader for electromagnetic interference (EMI) shielding and thermal enhancement.
  60. Sharma, Nirmal K., Package for integrated circuit with thermal vias and method thereof.
  61. Ryu,Jung Seok; Kim,Pyoung Wan, Package substrate and semiconductor package using the same.
  62. Moxham,Stephen F., Semiconductor component and system having stiffener and circuit decal.
  63. Moxham,Stephen F., Semiconductor component having stiffener, circuit decal and terminal contacts.
  64. Moxham,Stephen F., Semiconductor component having stiffener, stacked dice and circuit decals.
  65. Pendse, Rajendra D., Semiconductor device and method of forming pad layout for flipchip semiconductor die.
  66. Corisis, David J., Semiconductor die package.
  67. Lee, Ho-Cheol, Semiconductor integrated circuit having pads layout for increasing signal integrity and reducing chip size.
  68. Kim, Sang Hai, Semiconductor package and method for fabricating the same.
  69. Prindiville, Casey; Jiang, Tongbi; Street, Bret, Semiconductor packages and methods for making the same.
  70. Darveaux, Robert Francis; St. Amand, Roger D.; Perelman, Vladimir, Stackable package and method.
  71. Darveaux, Robert Francis; St. Amand, Roger D.; Perelman, Vladimir, Stackable package and method.
  72. Zhao, Sam Ziqun; Khan, Rezaur Rahman, Thermal improvement for hotspots on dies in integrated circuit packages.
  73. Zhao, Sam Ziqun; Khan, Reza-ur Rahman; Law, Edward; Papageorge, Marc, Thermally and electrically enhanced ball grid array package.
  74. Zhao, Sam Ziqun; Khan, Reaz-ur Rahman; Law, Edward; Papageorge, Marc, Thermally and electrically enhanced ball grid array packaging.
  75. Yoon, Tae-Sung, Wiring substrate for a semiconductor chip, and semiconducotor package having the wiring substrate.
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