초록 ▼

High quality dielectric layers, e.g., high-k dielectric layers comprised of at least one refractory or lanthanum series transition metal oxide or silicate, for use as gate insulator layers in in-laid metal gate MOS transistors and CMOS devices, are fabricated by forming an ultra-thin catalytic metal

High quality dielectric layers, e.g., high-k dielectric layers comprised of at least one refractory or lanthanum series transition metal oxide or silicate, for use as gate insulator layers in in-laid metal gate MOS transistors and CMOS devices, are fabricated by forming an ultra-thin catalytic metal layer, e.g., a monolayer thick layer of Pd or Pd, on a Si-based semiconductor substrate, electrolessly plating on the catalytic layer comprising at least one refractory or lanthanum series transition metal or metal-based dielectric precursor layer, such as of Zr and/or Hf, and then reacting the precursor layer with oxygen or with oxygen and the semiconductor substrate to form the at least one high-k metal oxide or silicate. The inventive methodology prevents, or at least substantially reduces, oxygen access to the substrate surface during at least the initial stage(s) of formation of the gate insulator layer, thereby minimizing deleterious formation of oxygen-induced surface states at the semiconductor substrate/gate insulator interface.

대표청구항 ▼

1. A method of forming a semiconductor device comprising at least one MOS transistor, comprising the sequential steps of:(a) providing a semiconductor substrate including at least a region of a first conductivity type and having a surface; (b) forming in said region of first conductivity type a pair

1. A method of forming a semiconductor device comprising at least one MOS transistor, comprising the sequential steps of:(a) providing a semiconductor substrate including at least a region of a first conductivity type and having a surface; (b) forming in said region of first conductivity type a pair of spaced-apart source and drain regions of a second, opposite conductivity type, said pair of spaced-apart source and drain regions extending to said substrate surface and including a pair of opposed, facing edges with a space therebetween; (c) forming a layer of an insulative material extending over said substrate surface; (d) exposing a portion of said substrate surface including said pair of facing edges of said pair of spaced-apart source and drain regions and said space therebetween; (e) forming an ultra-thin catalytic layer comprising at least one metal on said exposed portion of said substrate surface; (f) forming a layer of a gate insulator precursor material on said catalytic layer by electroless plating; (g) converting said layer of electrolessly-plated gate insulator precursor material into a layer of a gate insulator material; and (h) forming an electrically conductive gate electrode material in contact with said layer of gate insulator material.