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Methods of fabricating integrated circuit bonding pads including intermediate closed conductive layers having spaced apart insulating islands therein 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0663996 (2000-09-18)
우선권정보 KR-0059418 (1998-12-28)
발명자 / 주소
  • Soo-cheol Lee KR
  • Jong-hyon Ahn KR
  • Hyae-ryoung Lee KR
출원인 / 주소
  • Samsung Electronics Co., Ltd. KR
대리인 / 주소
    Myers Bigel Sibley & Sajovec
인용정보 피인용 횟수 : 11  인용 특허 : 19

초록

Bonding pads for integrated circuits include first and second spaced apart conductive layers, a third continuous conductive layer between the first and second spaced apart conductive layers and an array of spaced apart insulating islands in the third continuous conductive layer that extend therethro

대표청구항

1. A method of fabricating an internal structure of a bonding pad for an integrated circuit comprising the steps of:forming an underlying conductive layer on an integrated circuit substrate; forming a continuous conductive layer on the underlying conductive layer and electrically connected thereto,

이 특허에 인용된 특허 (19)

  1. Chittipeddi Sailesh ; Ryan Vivian, Bond pad design for integrated circuits.
  2. Wong Richard J., Bond pad having vias usable with antifuse process technology.
  3. Zhao Bin, Bonding pad and support structure and method for their fabrication.
  4. Hsiao Ming-Shan,TWX, Bonding pad structure and method thereof.
  5. Heim Dorothy A. (San Jose CA), Composite bond pads for semiconductor devices.
  6. Shiue Ruey-Yun (Hsin-Chu TWX) Wu Wen-Teng (Hsin-Chu TWX) Shieh Pi-Chen (Hsinchu TWX) Liu Chin-Kai (Hsin-Chu TWX), Method of forming bond pad structure for the via plug process.
  7. Eichelberger Charles W. (Schenectady NY), Multichip integrated circuit modules.
  8. Hsuan Min-Chih,TWX ; Liou Fu-Tai,TWX, Package-free bonding pad structure.
  9. Bryant Frank R. (Denton TX) Chen Fusen E. (Milpitas CA), Semiconductor bond pad structure and method.
  10. Tanaka Kazuo,JPX, Semiconductor device and a method for making the same that provide arrangement of a connecting region for an external connecting terminal.
  11. Fujiki Noriaki,JPX ; Yamashita Takashi,JPX, Semiconductor device and bonding pad structure therefor.
  12. Ito Kazunori,JPX ; Irinoda Mitsugu,JPX ; Ueno Kaichi,JPX ; Ishida Mamoru,JPX ; Kuroda Takahiko,JPX, Semiconductor device and manufacturing method for the same.
  13. Sato Hisakatsu,JPX, Semiconductor device having a multi-latered wiring structure.
  14. Satoh Shinichi (Hyogo JPX) Ozaki Hiroji (Hyogo JPX) Kimura Hiroshi (Hyogo JPX) Wakamiya Wataru (Hyogo JPX) Tanaka Yoshinori (Hyogo JPX), Semiconductor device having bonding pad comprising buffer layer.
  15. Lee Sueng-Rok,KRX ; Kim Myung-Sung,KRX ; Lee Yunhee,KRX ; Kim Manjun,KRX, Semiconductor device having multi-layered pad and a manufacturing method thereof.
  16. Nozaki Masahiko (Hyogo JPX), Semiconductor device structure including multiple interconnection layers with interlayer insulating films.
  17. Abe Masahiro (Yokohama JPX) Aoyama Masaharu (Fujisawa JPX) Ajima Takashi (Kamakura JPX) Yonezawa Toshio (Yokosuka JPX), Semiconductor device with an improved bonding section.
  18. Lu Chang-Ming,TWX ; Lu Shu-Ying,TWX, Structure of a bonding pad for semiconductor devices.
  19. Moslehi Mehrdad M., Ultra high-speed chip semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectrics.

이 특허를 인용한 특허 (11)

  1. Hébert, François; Bhalia, Anup, Copper bonding compatible bond pad structure and method.
  2. Hébert, François; Bhalla, Anup, Copper bonding compatible bond pad structure and method.
  3. Hébert, François; Bhalla, Anup, Copper bonding method.
  4. Lin, Ying-Hsi, Integrated circuit device having pads structure formed thereon and method for forming the same.
  5. Lin, Ying-Hsi, Integrated circuit device having pads structure formed thereon and method for forming the same.
  6. Lin, Ying-Hsi, Integrated circuit device having pads structure formed thereon and method for forming the same.
  7. Kuo,Yian Liang; Lin,Yu Chang, Integrated circuit package bond pad having plurality of conductive members.
  8. Bhalla, Anup; Pan, Ji; Ng, Daniel, Junction barrier Schottky diode with enforced upper contact structure and method for robust packaging.
  9. Ohta, Hiroyuki; Miura, Hideo; Sato, Kazushige; Kimura, Takeshi; Masuda, Hiyoo, Semiconductor device and method of fabricating same.
  10. Yamazaki, Yasushi, Semiconductor device having a bonding pad structure including an annular contact.
  11. Liang, Zhongning; Lous, Erik Jan, Semiconductor device with isolated intermetal dielectrics.
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