초록 ▼

A push-pull output buffer for use with an integrated circuit, such as a CMOS device, uses a driver gate voltage Feedback loop to control slew rate of the driver and reduce crowbar current. The feedback loop is coupled with the driver's control gate and functions to drive the gate up to an initial, i

A push-pull output buffer for use with an integrated circuit, such as a CMOS device, uses a driver gate voltage Feedback loop to control slew rate of the driver and reduce crowbar current. The feedback loop is coupled with the driver's control gate and functions to drive the gate up to an initial, intermediate level of voltage. A delay circuit coupled between the driver control gate and the buffer input delays the delivery of a control signal that couples the driver control gate to a higher level of voltage, such that an external load connected to the buffer's output is also driven to a higher level. A one way switch circuit coupled between the delay circuit and the feedback loop prevents interference there between until the higher level of voltage is applied to the control gate.

대표청구항 ▼

1. A CMOS push-pull output buffer having an input, and having an output for driving a load, comprising:a pull up section having a first controllable current driver for pulling up the voltage of said buffer output; a pull down section having a second controllable current driver for pulling down the v

1. A CMOS push-pull output buffer having an input, and having an output for driving a load, comprising:a pull up section having a first controllable current driver for pulling up the voltage of said buffer output; a pull down section having a second controllable current driver for pulling down the voltage of said buffer output; and first and second slew rate control circuits respectively associated with said first and second current drivers for controlling the rate at which the associated current driver changes the voltage at said buffer output, each of said slew rate control circuits including: (a) first voltage supply circuit for supplying a first, intermediate level of control voltage to the associated current driver, (b) a second voltage supply circuit for supplying a second level of control voltage to said associated current driver higher than said intermediate level, (c) a delay circuit for delaying the delivery of said second level of voltage to said associated current driver, and (d) a logic circuit for controlling said first and second voltage supply circuits.