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Configurable processor system unit 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-001/00
출원번호 US-0172918 (1998-10-14)
발명자 / 주소
  • Steven Paul Winegarden
  • Bart Reynolds
  • Brian Fox
  • Jean-Didier Allegrucci
  • Sridhar Krishnamurthy
  • Danesh Tavana
  • Arye Ziklik
  • Andreas Papaliolios
  • Stanley S. Yang
  • Fung Fung Lee
출원인 / 주소
  • Triscend Corporation
대리인 / 주소
    Blakely, Sokoloff, Taylor & Zafman LLP
인용정보 피인용 횟수 : 194  인용 특허 : 53

초록

The configurable processor system includes a processor, an internal system bus, and a programmable logic all interconnected via the internal system bus, on a single integrated circuit.

대표청구항 ▼

1. A configurable processor system unit comprising:a processor; at least one region of random access memory (RAM) based dynamically configurable volatile programmable logic; and a bus coupling the processor and the at least one region of programmable logic; wherein the processor, the programmable lo

이 특허에 인용된 특허 (53)

  1. Yazdy Farid A., Address and data bus arbiter for pipelined transactions on a split bus.
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  2. Murakami Tokumichi (Kanagawa JPX) Kamizawa Koh (Kanagawa JPX) Katoh Yoshiaki (Kanagawa JPX) Ohira Hideo (Kanagawa JPX) Kameyama Masatoshi (Kanagawa JPX) Kinjo Naoto (Kanagawa JPX), Address control and generating system for digital signal-processor.
    상세보기
  3. Freeman Ross H. (San Jose CA) Hsieh Hung-Cheng (Sunnyvale CA), Circuit for selecting a bit in a look-up table.
    상세보기
  4. Freeman ; deceased Ross H. (late of San Jose CA by Dennis Hersey ; executor), Configurable electrical circuit having configurable logic elements and configurable interconnects.
    상세보기
  5. Freeman Ross H. (San Jose CA), Configurable electrical circuit having configurable logic elements and configurable interconnects.
    상세보기
  6. Young Steven P. ; New Bernard J. ; Camilleri Nicolas John ; Bauer Trevor J. ; Bapat Shekhar ; Chaudhary Kamal ; Krishnamurthy Sridhar, Configurable logic element with fast feedback paths.
    상세보기
  7. Freeman Ross H. (San Jose CA) Hsieh Hung-Cheng (Sunnyvale CA), Distributed memory architecture for a configurable logic array and method for using distributed memory.
    상세보기
  8. Freeman Ross H. (San Jose CA) Hsieh Hung-Cheng (Sunnyvale CA), Distributed memory architecture for a configurable logic array and method for using distribution memory.
    상세보기
  9. Erickson Charles R. ; Tavana Danesh ; Holen Victor A., Encryption of configuration stream.
    상세보기
  10. Young Steven P. ; New Bernard J. ; Camilleri Nicolas John ; Bauer Trevor J. ; Bapat Shekhar ; Chaudhary Kamal ; Krishnamurthy Sridhar, FPGA CLE with two independent carry chains.
    상세보기
  11. Tavana Danesh (Mountain View CA) Yee Wilson K. (Tracy CA) Holen Victor A. (Saratoga CA), FPGA architecture with repeatable tiles including routing matrices and logic matrices.
    상세보기
  12. Tavana Danesh ; Yee Wilson K. ; Holen Victor A., FPGA architecture with repeatable titles including routing matrices and logic matrices.
    상세보기
  13. Young Steven P. ; Bauer Trevor J. ; Chaudhary Kamal ; Krishnamurthy Sridhar, FPGA repeatable interconnect structure with bidirectional and unidirectional interconnect lines.
    상세보기
  14. Bapat Shekhar ; Krishnamurthy Sridhar, High speed bidirectional bus with multiplexers.
    상세보기
  15. Young Steven P. ; Chaudhary Kamal ; Bapat Shekhar ; Krishnamurthy Sridhar ; Costello Philip D., High speed bus with tree structure for selecting bus driver.
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  16. Tavana Danesh (Mountain View CA), I/O interface cell for use with optional pad.
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  17. Tavana Danesh ; Yee Wilson K. ; Trimberger Stephen M., Integrated circuit with field programmable and application specific logic areas.
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  18. Tavana Danesh ; Yee Wilson K. ; Trimberger Stephen M., Integrated circuit with field programmable and application specific logic areas.
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  19. Haines Ralph Warren ; O'Neill Dan Craig ; Pries Stephen C. ; Miller William V. ; Waterson Kent B. ; Weinman David S. ; Shay Michael J. ; Pang Jianhua Helen ; Herrington Daniel R. ; Marley Brian J. ; , Integrated circuit with multiple functions sharing multiple internal signal buses according to distributed bus access an.
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  20. Wong Dale ; Phillips Christopher E. ; Cooke Laurence H., Integrated processor and programmable data path chip for reconfigurable computing.
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  21. Lee Fung Fung, Interleaved interconnect for programmable logic array devices.
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  22. Lane Christopher F. (Campbell CA) Reddy Srinivas T. (Santa Clara CA) Wang Bonnie I. (Cupertino CA), Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices.
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  23. Papaliolios Andreas, Method and apparatus for a power-on-reset system.
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  24. New Bernard J. ; Tavana Danesh, Method and circuit for using a function generator of a programmable logic device to implement carry logic functions.
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  25. Platteter Dale T. (Fairport NY) Westfall Robert S. (Rochester NY) Carter Jeff C. (Fairport NY), Method for selectively loading bootable fiber to control apparatus based upon the corresponding bootable attributes.
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  26. Cedar Yoram ; Ziklik Arye, Microcontroller accessible macrocell.
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  27. Pinai Felix ; Phan Manhtien, Multiprocessor arrangement including bus arbitration scheme involving plural CPU clusters that address each other as "p.
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  28. Gunter Thomas G. (Austin TX) Musa Fuad H. (Austin TX) Wilder ; Jr. Wm. B. (Austin TX) Wiles Michael F. (Round Rock TX), On chip ram interconnect to MPU bus.
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  29. Papaliolios Andreas, Output pre-driver for reducing totem pole current.
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  30. Cedar Yoram (Cupertino CA) Ziklik Arye (Sunnyvale CA) Shubat Alex (Fremont CA), Page register with a don\t care function.
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  31. Monroe Midori Jean,CAX ; Messer Dion Dee, Parallel processing building block chip.
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  32. Patel Rakesh H. ; Norman Kevin A., Partially reconfigurable programmable logic device.
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  33. Lee Yu-Hua,TWX ; Wu James,TWX, Passivation etching procedure, using a polysilicon stop layer, for repairing embedded DRAM cells.
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  34. Ziklik Arye (Sunnyvale CA) Shubat Alexander (Fremont CA) Cedar Yoram (Cupertino CA) Pasternak John H. (Fremont CA), Peripheral port with volatile and non-volatile configuration.
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  35. Normoyle Kevin B. ; Ebrahim Zahir ; Nishtala Satyanarayana ; Van Loo William C. ; Coffin ; III Louis F., Pipelined distributed bus arbitration system.
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  36. Birkner John M. (Sunnyvale CA) Tavana Danesh M. (San Jose CA) Chan Andrew K. (Milpitas CA) Wong Sing Y. (Sunnyvale CA), Programmable array logic cell.
    상세보기
  37. Freeman ; deceased Ross H. (late of San Jose CA by Dennis Hersey ; executor) Duong Khue (San Jose CA) Hsieh Hung-Cheng (Sunnyvale CA) Erickson Charles R. (Fremont CA) Carter William S. (Santa Clara C, Programmable connector for programmable logic device.
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  38. Cliff Richard G. ; Heile Francis B. ; Huang Joseph ; Lee Fung Fung ; McClintock Cameron ; Mendel David W. ; Pedersen Bruce B. ; Reddy Srinivas T. ; Sung Chiakang ; Veenstra Kerry ; Wang Bonnie I., Programmable logic device architectures.
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  39. Patel Rakesh H. (Santa Clara CA) Wong Myron W. (San Jose CA), Programmable logic device with redundant circuitry.
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  40. Lee Fung Fung, Programmable logic device with two dimensional memory addressing.
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  41. Krishnamurthy Sridhar ; Bapat Shekhar, Programmably bidirectional buffered interconnect circuit.
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  42. Tavana Danesh (Mountain View CA), Read and writable data bus particularly for programmable logic devices.
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  43. Smith Stephen J., Reconfigurable computer architecture using programmable logic devices.
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  44. Ebeling William Henry Carl ; Cronquist Darren Charles ; Franklin Paul David, Reconfigurable computing architecture for providing pipelined data paths.
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  45. Gatherer Alan ; Lemonds ; Jr. Carl E. ; Hocevar Dale E. ; Hung Ching-Yu, Reconfigurable multiply-accumulate hardware co-processor unit.
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  46. Upton Eric L., Reconfigurable processor for executing successive function sequences in a processor operation.
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  47. Sawase Terumi,JPX ; Noguchi Kouki,JPX ; Nakamura Hideo,JPX ; Akao Yasushi,JPX ; Baba Shiro,JPX ; Hagiwara Yoshimune,JPX, Single-chip semiconductor integrated circuit device and microcomputer integrated on a semiconductor chip.
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  48. Jenkins ; IV Jesse H., Slew rate selection circuit for a programmable device.
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  49. Topolewski Todd J. (Oakland CA) Weir Christine M. (Santa Cruz CA) Reynolds Bart (Campbell CA) Smuts Julia M. (San Jose CA) Wynn Pardner (San Jose CA) Trimberger Stephen M. (San Jose CA), Structure and method for manually controlling automatic configuration in an integrated circuit logic block array.
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  50. Sibigtroth James M. (Round Rock TX), System for securing a data processing system and method of operation.
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  51. Cliff Richard G. ; Reddy Srinivas T. ; Papaliolios Andreas, Techniques for programming programmable logic array devices.
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  52. Cliff Richard G. ; Reddy Srinivas T. ; Veenstra Kerry ; Papaliolios Andreas ; Sung Chiakang ; Terrill Richard Shaw ; Raman Rina ; Bielby Robert Richard Noel, Techniques for programming programmable logic array devices.
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  53. Lee Sherman, User-removable central processing unit card for an electrical device.
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이 특허를 인용한 특허 (194)

  1. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
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  4. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
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  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
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  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
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  19. Winegarden, Steven P.; Ziklik, Arye; Knapp, Steven K., Bus mastering debugging system for integrated circuits.
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