$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Reconfigurable device having programmable interconnect network suitable for implementing data paths 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-019/177
출원번호 US-0880018 (2001-06-14)
우선권정보 JP-0184598 (2000-06-15)
발명자 / 주소
  • Shogo Nakaya JP
출원인 / 주소
  • NEC Corporation JP
대리인 / 주소
    Sughrue Mion, PLLC
인용정보 피인용 횟수 : 157  인용 특허 : 7

초록

A reconfigurable device includes a plurality of function cells and a programmable interconnect network which programmably connects the function cells. The programmable interconnect network includes horizontal programmable interconnect ways and vertical programmable interconnect ways. Each horizontal

대표청구항

ches programmably connects/disconnects the connection between the line segments that are connected thereto.

이 특허에 인용된 특허 (7)

  1. Kaptanoglu Sinan, Block symmetrization in a field programmable gate array.
  2. Kean Thomas A. (Edinburgh GB6), Hierarchically connectable configurable cellular array.
  3. Trimberger Stephen M., PLD having a window pane architecture with segmented and staggered interconnect wiring between logic block arrays.
  4. Clinton Kim P. N. (Essex Junction VT) Gould Scott W. (South Burlington VT) Hartman Steven P. (Jericho VT) Iadanza Joseph A. (Hinesburg VT) Keyser ; III Frank R. (Colchester VT) Millham Eric E. (St. G, Programmable array interconnect network.
  5. Leong William (San Francisco CA) McClintock Cameron (Mountain View CA) Cliff Richard G. (Milpitas CA), Programmable logic array integrated circuits with interconnection conductors of overlapping extent.
  6. Camarota Rafael C. (San Jose CA) Furtek Frederick C. (Menlo Park CA) Ho Walford W. (Saratoga CA) Browder Edward H. (Saratoga CA), Programmable logic cell and array with bus repeaters.
  7. Mavis David G., Tiered routing architecture for field programmable gate arrays.

이 특허를 인용한 특허 (157)

  1. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  2. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  3. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  4. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
  7. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
  8. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  9. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  10. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  11. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
  12. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  13. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  14. Redgrave, Jason; Schmit, Herman, Barrel shifter implemented on a configurable integrated circuit.
  15. Schmit,Herman; Redgrave,Jason, Clock distribution in a configurable IC.
  16. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
  17. Schmit, Herman; Huang, Randy Renfu, Configurable IC having a routing fabric with storage elements.
  18. Teig, Steven, Configurable IC having a routing fabric with storage elements.
  19. Teig, Steven; Schmit, Herman; Huang, Randy Renfu, Configurable IC having a routing fabric with storage elements.
  20. Teig, Steven; Schmit, Herman; Huang, Randy Renfu, Configurable IC having a routing fabric with storage elements.
  21. Teig, Steven; Schmit, Herman; Redgrave, Jason, Configurable IC having a routing fabric with storage elements.
  22. Schmit, Herman; Teig, Steven; Hutchings, Brad; Huang, Randy Renfu; Redgrave, Jason, Configurable IC with configurable routing resources that have asymmetric input and/or outputs.
  23. Schmit, Herman; Teig, Steven; Hutchings, Brad; Huang, Randy Renfu; Redgrave, Jason, Configurable IC with configuration logic resources that have asymmetric inputs and/or outputs.
  24. Teig, Steven; Redgrave, Jason, Configurable IC with error detection and correction circuitry.
  25. Teig, Steven; Schmit, Herman; Redgrave, Jason; Chandra, Vikas, Configurable IC with interconnect circuits that also perform storage operations.
  26. Teig,Steven; Schmit,Herman; Redgrave,Jason; Chandra,Vikas, Configurable IC with interconnect circuits that also perform storage operations.
  27. Hutchings,Brad; Schmit,Herman; Teig,Steven, Configurable IC with interconnect circuits that have select lines driven by user signals.
  28. Schmit, Herman; Redgrave, Jason, Configurable IC with large carry chains.
  29. Schmit, Herman; Teig, Steven; Hutchings, Brad; Huang, Randy Renfu, Configurable IC with logic resources with offset connections.
  30. Schmit, Herman; Teig, Steven; Hutchings, Brad; Huang, Randy Renfu, Configurable IC with routing circuits with offset connections.
  31. Schmit,Herman; Teig,Steven; Hutchings,Brad; Huang,Randy Renfu, Configurable IC with routing circuits with offset connections.
  32. Redgrave, Jason; Schmit, Herman; Teig, Steven; Hutchings, Brad L.; Huang, Randy R., Configurable IC'S with large carry chains.
  33. Schmit,Herman; Teig,Steven; Hutchings,Brad; Huang,Randy Renfu; Redgrave,Jason, Configurable IC's with configurable logic resources that have asymetric inputs and/or outputs.
  34. Teig, Steven; Redgrave, Jason, Configurable IC's with dual carry chains.
  35. Schmit,Herman; Teig,Steven; Hutchings,Brad; Huang,Randy Renfu, Configurable IC's with logic resources with offset connections.
  36. Teig, Steven; Caldwell, Andrew; Redgrave, Jason, Configurable ICs that conditionally transition through configuration data sets.
  37. Schmit, Herman; Butts, Michael; Hutchings, Brad L.; Teig, Steven, Configurable circuits, IC's and systems.
  38. Schmit, Herman; Butts, Michael; Hutchings, Brad L.; Teig, Steven, Configurable circuits, IC's, and systems.
  39. Schmit, Herman; Butts, Michael; Hutchings, Brad L.; Teig, Steven, Configurable circuits, IC's, and systems.
  40. Schmit,Herman; Butts,Michael; Hutchings,Brad L.; Teig,Steven, Configurable circuits, IC's, and systems.
  41. Schmit,Herman; Butts,Michael; Hutchings,Brad L.; Teig,Steven, Configurable circuits, IC's, and systems.
  42. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
  43. Schmit, Herman; Caldwell, Andrew; Teig, Steven, Configurable integrated circuit with a 4-to-1 multiplexer.
  44. Rohe, Andre; Teig, Steven, Configurable integrated circuit with built-in turns.
  45. Rohe, Andre; Teig, Steven, Configurable integrated circuit with built-in turns.
  46. Rohe, Andre; Teig, Steven, Configurable integrated circuit with different connection schemes.
  47. Teig, Steven; Redgrave, Jason; Horel, Timothy, Configurable integrated circuit with error correcting circuitry.
  48. Schmit,Herman; Teig,Steven; Hutchings,Brad, Configurable integrated circuit with parallel non-neighboring offset connections.
  49. Ikeda,Kenji; Shimura,Hiroshi; Sato,Tomoyoshi, Configurable interconnection of multiple different type functional units array including delay type for different instruction processing.
  50. Schmit,Herman; Teig,Steven, Configurable logic circuits with commutative properties.
  51. Teig, Steven; Ebeling, Christopher D.; Voogel, Martin; Caldwell, Andrew, Configurable storage elements.
  52. Voogel, Martin; Teig, Steven; Chanack, Thomas S.; Caldwell, Andrew; Ko, Jung; Chandler, Trevis, Configurable storage elements.
  53. Voogel, Martin; Teig, Steven; Chandler, Trevis, Configurable storage elements.
  54. Chandler, Trevis; Redgrave, Jason; Voogel, Martin, Configuration context switcher.
  55. Chandler, Trevis; Entjer, Joe; Voogel, Martin; Redgrave, Jason, Configuration context switcher with a clocked storage element.
  56. Chandler, Trevis; Entjer, Joe; Voogel, Martin; Redgrave, Jason, Configuration context switcher with a clocked storage element.
  57. Voogel, Martin; Redgrave, Jason; Chandler, Trevis, Configuration context switcher with a latch.
  58. Redgrave, Jason; Voogel, Martin; Teig, Steven, Controllable storage elements for an IC.
  59. Redgrave, Jason; Voogel, Martin; Teig, Steven, Controllable storage elements for an IC.
  60. Redgrave, Jason; Voogel, Martin; Teig, Steven, Controllable storage elements for an IC.
  61. Tsunoda, Takanobu; Atwood, Bryan; Takada, Masashi; Tanaka, Hiroshi, Data processor with internal memory structure for processing stream data.
  62. Schmit, Herman; Redgrave, Jason, Embedding memory between tile arrangement of a configurable IC.
  63. Schmit,Herman; Redgrave,Jason, Embedding memory between tile arrangement of a configurable IC.
  64. Schmit,Herman; Redgrave,Jason, Embedding memory within tile arrangement of a configurable IC.
  65. Schmit, Herman; Redgrave, Jason, Embedding memory within tile arrangement of an integrated circuit.
  66. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
  67. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  68. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  69. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  70. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  71. Konda, Venkat, Fast scheduling and optimization of multi-stage hierarchical networks.
  72. Konda, Venkat, Fast scheduling and optmization of multi-stage hierarchical networks.
  73. Wasson, Stephen L.; Box, Brian A.; Rudosky, John M.; Kelem, Steven Hennick, Hierarchically-scalable reconfigurable integrated circuit architecture with unit delay modules.
  74. Hutchings, Brad; Schmit, Herman; Teig, Steven, Hybrid configurable circuit for a configurable IC.
  75. Hutchings,Brad; Schmit,Herman; Redgrave,Jason, Hybrid logic/interconnect circuit in a configurable IC.
  76. Pugh, Daniel J.; Caldwell, Andrew, IC that efficiently replicates a function to save logic and routing resources.
  77. Nagrani, Mehul; Wong, Victor; Wright, Jeffrey P., Individual I/O modulation in memory devices.
  78. Nagrani,Mehul; Wong,Victor; Wright,Jeffrey P., Individual I/O modulation in memory devices.
  79. Nagrani,Mehul; Wong,Victor; Wright,Jeffrey P., Individual I/O modulation in memory devices.
  80. Qian, Qi-De, Integrated circuits having in-situ constraints.
  81. Ray,Nicholas John Charles; Olgiati,Andrea; Stansfield,Anthony I.; Marshall,Alan D, Loosely-biased heterogeneous reconfigurable arrays.
  82. Stansfield,Anthony I., Loosely-biased heterogeneous reconfigurable arrays.
  83. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  84. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  85. Redgrave, Jason; Schmit, Herman, Method and apparatus for accessing contents of memory cells.
  86. Redgrave, Jason, Method and apparatus for accessing stored data in a reconfigurable IC.
  87. Redgrave,Jason, Method and apparatus for accessing stored data in a reconfigurable IC.
  88. Caldwell, Andrew; Schmit, Herman; Teig, Steven, Method and apparatus for decomposing functions in a configurable IC.
  89. Caldwell, Andrew; Schmit, Herman; Teig, Steven, Method and apparatus for decomposing functions in a configurable IC.
  90. Caldwell, Andrew; Teig, Steven, Method and apparatus for function decomposition.
  91. Rohe, Andre; Teig, Steven, Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit.
  92. Rohe, Andre; Teig, Steven, Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit.
  93. Rohe, Andre; Teig, Steven, Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit.
  94. Redgrave, Jason; Caldwell, Andrew; Teig, Steven, Method and apparatus for performing an operation with a plurality of sub-operations in a configurable IC.
  95. Redgrave, Jason; Hutchings, Brad; Schmit, Herman; Teig, Steven, Method and apparatus for performing shifting in an integrated circuit.
  96. Pugh, Daniel J., Method and apparatus for performing two's complement multiplication.
  97. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
  98. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
  99. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  100. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  101. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  102. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  103. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  104. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  105. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  106. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  107. Loboda,Mark Jon; Hwang,Byung Keun, Method for producing hydrogenated silicon-oxycarbide films.
  108. Schmit, Herman; Butts, Michael; Hutchings, Brad L.; Teig, Steven, Method of mapping a user design defined for a user design cycle to an IC with multiple sub-cycle reconfigurable circuits.
  109. Schmit, Herman; Butts, Michael; Hutchings, Brad L.; Teig, Steven, Non-sequentially configurable IC.
  110. Schmit, Herman; Butts, Michael; Hutchings, Brad L.; Teig, Steven, Non-sequentially configurable IC.
  111. Rohe, Andre; Teig, Steven; Schmit, Herman; Redgrave, Jason; Caldwell, Andrew, Operational time extension.
  112. Rohe, Andre; Teig, Steven; Schmit, Herman; Redgrave, Jason; Caldwell, Andrew, Operational time extension.
  113. Konda, Venkat, Optimization of multi-stage hierarchical networks for practical routing applications.
  114. Konda, Venkat, Optimization of multi-stage hierarchical networks for practical routing applications.
  115. Pugh, Daniel J.; Redgrave, Jason; Caldwell, Andrew, Performing mathematical and logical operations in multiple sub-cycles.
  116. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
  117. Kao,Oliver C.; Kunnari,Nancy D., Programmable logic auto write-back.
  118. Aoki, Takeshi; Ikeda, Takayuki; Kurokawa, Yoshiyuki; Kozuma, Munehiro, Programmable logic device and semiconductor device.
  119. Aoki, Takeshi; Ikeda, Takayuki; Kurokawa, Yoshiyuki; Kozuma, Munehiro, Programmable logic device and semiconductor device.
  120. Hutton,Michael D.; Lewis,David, Programmable routing structures providing shorter timing delays for input/output signals.
  121. Voogel, Martin; Redgrave, Jason; Chandler, Trevis, Reading configuration data from internal storage node of configuration storage circuit.
  122. Teig, Steven; Schmit, Herman; Redgrave, Jason, Reconfigurable IC that has sections running at different looperness.
  123. Teig,Steven; Schmit,Herman; Redgrave,Jason, Reconfigurable IC that has sections running at different looperness.
  124. Teig, Steven; Schmit, Herman; Redgrave, Jason, Reconfigurable IC that has sections running at different reconfiguration rates.
  125. Teig, Steven; Schmit, Herman; Redgrave, Jason, Reconfigurable IC that has sections running at different reconfiguration rates.
  126. Teig,Steven; Schmit,Herman; Redgrave,Jason, Reconfigurable IC that has sections running at different reconfiguration rates.
  127. Kitaoka, Toshirou, Reconfigurable semiconductor integrated circuit.
  128. Kitaoka, Toshirou, Reconfigurable semiconductor integrated circuit.
  129. Caldwell,Andrew; Redgrave,Jason, Replacing circuit design elements with their equivalents.
  130. Higuchi, Koji, Semiconductor device and package with bit cells and power supply electrodes.
  131. Caldwell, Andrew; Teig, Steven, Sequential delay analysis by placement engines.
  132. Master,Paul L.; Watson,John, Storage and delivery of device features.
  133. Redgrave, Jason, Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements.
  134. Redgrave, Jason, Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements.
  135. Redgrave, Jason, Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements.
  136. Redgrave,Jason, Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements.
  137. Redgrave,Jason; Hutchings,Brad; Schmit,Herman; Teig,Steven, Sub-cycle configurable hybrid logic/interconnect circuit.
  138. Schmit, Herman; Caldwell, Andrew; Hutchings, Brad; Redgrave, Jason; Teig, Steven, System and method for providing a virtual memory architecture narrower and deeper than a physical memory architecture.
  139. Schmit, Herman; Caldwell, Andrew; Hutchings, Brad; Redgrave, Jason; Teig, Steven, System and method for providing a virtual memory architecture narrower and deeper than a physical memory architecture.
  140. Schmit, Herman; Teig, Steven; Hutchings, Brad, System and method for providing more logical memory ports than physical memory ports.
  141. Schmit, Herman; Teig, Steven; Hutchings, Brad, System and method for providing more logical memory ports than physical memory ports.
  142. Schmit, Herman; Pugh, Daniel J.; Teig, Steven, System and method of mapping memory blocks in a configurable integrated circuit.
  143. Schmit, Herman; Pugh, Daniel J.; Teig, Steven, System and method of providing a memory hierarchy.
  144. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
  145. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
  146. Teig, Steven; Caldwell, Andrew, Timing operations in an IC with configurable circuits.
  147. Teig, Steven; Caldwell, Andrew, Timing operations in an IC with configurable circuits.
  148. Pugh, Daniel J.; Schmit, Herman; Redgrave, Jason; Caldwell, Andrew, Use of hybrid interconnect/logic circuits for multiplication.
  149. Redgrave, Jason, User registers implemented with routing circuits in a configurable IC.
  150. Redgrave, Jason, User registers implemented with routing circuits in a configurable IC.
  151. Redgrave, Jason; Schmit, Herman, User registers implemented with routing circuits in a configurable IC.
  152. Redgrave, Jason, Users registers implemented with routing circuits in a configurable IC.
  153. Schmit,Herman; Redgrave,Jason, Users registers in a reconfigurable IC.
  154. Schmit, Herman; Teig, Steven, VPA interconnect circuit.
  155. Schmit,Herman; Teig,Steven, VPA logic circuits.
  156. Hutchings, Brad, Variable width management for a memory of a configurable IC.
  157. Hutchings, Brad, Variable width writing to a memory of an IC.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로