초록 ▼

An apparatus and method for accelerating interpreters, interpretive environments, may manage pinning of a processor cache closest to a processor. An instruction set implementing a virtual machine may store each instruction in a single cache line as a compiled, linked loaded image. After loading, the

An apparatus and method for accelerating interpreters, interpretive environments, may manage pinning of a processor cache closest to a processor. An instruction set implementing a virtual machine may store each instruction in a single cache line as a compiled, linked loaded image. After loading, the cache is pinned, disabled from flushing the contents or replacing the contents of any cache line. A fast load may flush the cache and run an application containing the entire virtual machine instruction set. A pin manager may be hooked into a scheduler in a multi-tasking operating system to load, pin, and unpin the processor cache as rapidly as needed. Thus, the processor cache may be available for general use, except when pinned for use by a virtual machine, such as an interpretive environment. Level-1 caches integrated into central processing units, particularly instruction caches or code caches are ideally suited to implementation of the invention.

대표청구항 ▼

1. An apparatus for programmatically managing a processor cache, the apparatus comprising:a processor for executing instructions; a memory device operably connected to the processor and containing executables comprising the instructions, wherein the executables include a virtual machine comprising a

1. An apparatus for programmatically managing a processor cache, the apparatus comprising:a processor for executing instructions; a memory device operably connected to the processor and containing executables comprising the instructions, wherein the executables include a virtual machine comprising a set of instructions and a pin manager; a processor cache operably connected to the memory device to receive and persistently store the instructions under independent programmatic control of the pin manager, the pin manager being executable by the processor; and the processor programmed to execute the pin manager, the pin manager to: determine loading of the set of instructions into the processor cache; and control the persistence of the instructions in the processor cache, wherein the persistence is a duration of the set of instructions in the processor cache.