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Semiconductor substrate and production method thereof 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-027/01
  • H01L-027/12
  • H01L-029/167
출원번호 US-0716429 (2000-11-21)
우선권정보 JP-0208033 (1998-07-23); JP-0208034 (1998-07-23); JP-0208035 (1998-07-23)
발명자 / 주소
  • Iku Shiota JP
출원인 / 주소
  • Canon Kabushiki Kaisha JP
대리인 / 주소
    Fitzpatrick, Cella, Harper & Scinto
인용정보 피인용 횟수 : 22  인용 특허 : 22

초록

In order to provide a semiconductor substrate that can be an SOI substrate suitable for production of high-frequency transistor, the semiconductor substrate is produced by a method of producing the semiconductor substrate having a step of bonding a first base having a semiconductor layer region to a

대표청구항

1. A semiconductor substrate having a semiconductor layer region comprising a single-crystal semiconductor through an insulating layer on a support substrate comprising a semiconductor, wherein the support substrate has a composition such that a semiconductor surface portion adjacent to the insulati

이 특허에 인용된 특허 (22)

  1. Christensen Todd Alan ; Sheets ; II John Edward, Buried patterned conductor planes for semiconductor-on-insulator integrated circuit.
  2. Moslehi Mehrdad M. (Los Altos CA), Direct gas-phase doping of semiconductor wafers using an organic dopant source of phosphorus.
  3. Lee Sahng Kyoo,KRX ; Park Sang Kyun,KRX, Method for fabricating semiconductor wafers.
  4. Inoue Shunsuke,JPX ; Miyawaki Mamoru,JPX ; Fukumoto Yoshihiko,JPX, Method for manufacturing semiconductor substrate.
  5. Sato Nobuhiko,JPX ; Yonehara Takao,JPX ; Sakaguchi Kiyofumi,JPX, Method for producing semiconductor substrate.
  6. Gaul Stephen J. (Melbourne FL) Rouse George V. (Indialantic FL), Method of fabricating SOI wafer with SiGe as an etchback film in a BESOI process.
  7. Kawasaki Tetuo (Katano JPX) Koretika Tetuhiro (Hirakata JPX) Kitabatake (Nara JPX) Hirao Takasi (Moriguchi JPX), Method of fabricating semiconductor thin film and a Hall-effect device.
  8. Nakagawa Tsutomu (Hyogo JPX), Method of making thyristor with a high tolerable bias voltage.
  9. Cheung Nathan W. ; Lu Xiang ; Hu Chenming, Method of separating films from bulk substrates by plasma immersion ion implantation.
  10. Yonehara Takao (Atsugi JPX) Yamagata Kenji (Kawasaki JPX), Process for preparing semiconductor substrate by bringing first and second substrates in contact.
  11. Sakaguchi Kiyofumi,JPX ; Yonehara Takao,JPX, Process for production of semiconductor substrate.
  12. Bruel Michel (Veurey FRX), Process for the production of thin semiconductor material films.
  13. Yamagata Kenji (Kawasaki JPX) Yonehara Takao (Atsugi JPX), Process of fabricating a semiconductor substrate.
  14. Chen Wei ; Sadana Devendra Kumar ; Taur Yuan, SOI CMOS structure.
  15. Okonogi Kensuke,JPX, SOI substrate having a high heavy metal gettering effect for semiconductor device.
  16. Begley Patrick A. ; Rivoli Anthony ; Bajor Gyorgy ; Lowther Rex E., Semi-insulating wafer.
  17. Yamaguchi Hitoshi (Nagoya JPX) Fujino Seiji (Toyota JPX) Hattori Tadashi (Okazaki JPX), Semiconductor device and manufacturing method therefor.
  18. Sakakibara Toshio (Nishio JPX) Yamaoka Masami (Anjo JPX), Semiconductor device with gradually varying doping levels to compensate for thickness variations.
  19. Yonehara Takao (Atsugi JPX), Semiconductor member and process for preparing semiconductor member.
  20. Hwang Jeong-Mo (Plano TX), Silicon on insulator device comprising improved substrate doping.
  21. Wollesen Donald L., Silicon-on-insulator configuration which is compatible with bulk CMOS architecture.
  22. Burr James B., Tunable threshold SOI device using isolated well structure for back gate.

이 특허를 인용한 특허 (22)

  1. Coleman,John Howard, Fabrication method for silicon-on defect layer in field-effect and bipolar transistor devices.
  2. Stuber, Michael A., Forming semiconductor structure with device layers and TRL.
  3. Stuber, Michael A., Forming semiconductor structure with device layers and TRL.
  4. Akselrod, Mark, Method for forming aluminum oxide material used in optical data storage.
  5. Reynaud, Patrick; Kerdiles, Sebastien; Delprat, Daniel, Method for manufacturing a semiconductor on insulator structure having low electrical losses.
  6. Reynaud, Patrick; Kerdiles, Sébastien; Delprat, Daniel, Method for manufacturing a semiconductor-on-insulator structure having low electrical losses.
  7. Reynaud, Patrick; Kerdiles, Sébastien; Delprat, Daniel, Method for manufacturing a semiconductor-on-insulator structure having low electrical losses, and corresponding structure.
  8. Akselrod,Mark S.; Akselrod,Anne E., Method for non-destructive measuring of radiation dose.
  9. Libbert, Jeffrey L.; Fei, Lu; Standley, Robert W., Methods for producing silicon on insulator structures having high resistivity regions in the handle wafer.
  10. Brindle, Chris N.; Stuber, Michael A.; Molin, Stuart B., Methods for the formation of a trap rich layer.
  11. Brindle, Chris; Stuber, Michael A.; Molin, Stuart B., Methods for the formation of a trap rich layer.
  12. Raskin, Jean Pierre; Lederer, Dimitri; Brunier, François, Process for manufacturing a multilayer structure made from semiconducting materials.
  13. Molin, Stuart B.; Stuber, Michael A.; Drucker, Mark, Redistribution layer contacting first wafer through second wafer.
  14. Stuber, Michael A.; Imthurn, George, Semiconductor structure with TRL and handle wafer cavities.
  15. Brindle, Chris; Stuber, Michael A.; Molin, Stuart B., Trap rich layer for semiconductor devices.
  16. Brindle, Christopher N.; Stuber, Michael A.; Molin, Stuart B., Trap rich layer for semiconductor devices.
  17. Arriagada, Anton; Stuber, Michael A.; Molin, Stuart B., Trap rich layer formation techniques for semiconductor devices.
  18. Arriagada, Anton; Stuber, Michael A.; Molin, Stuart B., Trap rich layer formation techniques for semiconductor devices.
  19. Arriagada, Anton; Stuber, Michael A.; Molin, Stuart B., Trap rich layer formation techniques for semiconductor devices.
  20. Arriagada, Anton; Brindle, Chris; Stuber, Michael A., Trap rich layer with through-silicon-vias in semiconductor devices.
  21. Arriagada, Anton; Brindle, Chris; Stuber, Michael A., Trap rich layer with through-silicon-vias in semiconductor devices.
  22. Arriagada, Anton; Brindle, Chris; Stuber, Michael A., Trap rich layer with through-silicon-vias in semiconductor devices.
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