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Semiconductor device 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/34
출원번호 US-0482337 (2000-01-14)
우선권정보 JP-0008584 (1999-01-18)
발명자 / 주소
  • Hajime Iizuka JP
출원인 / 주소
  • Shinko Electric Industries Co., Ltd. JP
대리인 / 주소
    Pennie & Edmonds LLP
인용정보 피인용 횟수 : 127  인용 특허 : 1

초록

A semiconductor device in which a plurality of semiconductor chips are consolidated into one and which is provided with at least a set of rerouting wiring lines formed so as to interconnect electrodes of the respective semiconductor chips, the electrodes having a function which is common to the resp

대표청구항

1. A semiconductor device comprising a plurality of semiconductor chips consolidated into one, each semiconductor chip having formed on its surface electrodes, a first insulation film formed so as to expose the electrodes, patterned rerouting wiring lines formed on the first insulation film to be co

이 특허에 인용된 특허 (1)

  1. Akagawa Masatoshi,JPX ; Higashi Mitsutoshi,JPX ; Iizuka Hajime,JPX ; Arai Takehiko,JPX, Semiconductor device having an element with circuit pattern thereon.

이 특허를 인용한 특허 (127)

  1. Lee, Jin-Yuan; Lo, Hsin-Jung, Chip assembly with interconnection by metal bump.
  2. Chou, Chien-Kang; Chou, Chiu-Ming; Lin, Li-Ren; Lo, Hsin-Jung, Chip package and method for fabricating the same.
  3. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip package with die and substrate.
  4. Lin, Mou-Shiung; Chou, Chiu-Ming, Chip structure.
  5. Lin, Mou-Shiung; Chou, Chiu-Ming, Chip structure.
  6. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang; Lo, Hsin-Jung, Chip structure.
  7. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  8. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  9. Kuo, Nick; Chou, Chiu-Ming; Chou, Chien-Kang; Lin, Chu-Fu, Chip structure with bumps and testing pads.
  10. Lin,Mou Shiung, Chip structure with redistribution traces.
  11. Lee, Jin-Yaun; Lin, Mou-Shiung; Huang, Ching-Cheng, Integrated chip package structure using ceramic substrate and method of manufacturing the same.
  12. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Integrated chip package structure using organic substrate and method of manufacturing the same.
  13. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Integrated chip package structure using silicon substrate and method of manufacturing the same.
  14. Lin, Mou-Shiung; Lee, Jin-Yuan, Integrated circuit and method for fabricating the same.
  15. Lin, Mou-Shiung; Lee, Jin-Yuan, Integrated circuit and method for fabricating the same.
  16. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  17. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  18. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  19. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  20. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  21. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  22. Yeoh, Terence Sern-Wei; Ives, Neil A., Isosurfacial three-dimensional imaging system and method.
  23. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Method for fabricating chip package with die and substrate.
  24. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  25. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  26. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  27. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  28. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  29. Lee, Jin-Yuan; Chen, Ying-chih, Method of wire bonding over active area of a semiconductor circuit.
  30. Park, Young-ju; Min, Jae-ho; Kim, Myeong-cheol; Kim, Dong-chan; Sim, Jae-hwang, Methods of forming semiconductor devices having narrow conductive line patterns.
  31. Lin, Mou-Shiung; Lee, Jin-Yuan, Non-cyanide gold electroplating for fine-line gold traces and gold pads.
  32. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection process and structures.
  33. Lin, Mou Shiung; Lee, Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  34. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  35. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  36. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  37. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  38. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  39. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  40. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  41. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  42. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  43. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  44. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  45. Lin, Mou Shiung; Lee, Jin Yuan, Post passivation interconnection schemes on top of IC chips.
  46. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chips.
  47. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chips.
  48. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chips.
  49. Lin, Mou-Shiung, Post passivation interconnection schemes on top of the IC chips.
  50. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
  51. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
  52. Lin,Mou Shiung, Post passivation interconnection schemes on top of the IC chips.
  53. Lin,Mou Shiung, Post passivation interconnection schemes on top of the IC chips.
  54. Lin,Mou Shiung, Post passivation interconnection schemes on top of the IC chips.
  55. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Post passivation interconnection schemes on top of the IC chips.
  56. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Post passivation interconnection schemes on top of the IC chips.
  57. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Post passivation interconnection schemes on top of the IC chips.
  58. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
  59. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
  60. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
  61. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
  62. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
  63. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
  64. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
  65. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
  66. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection structures.
  67. Lin, Mou-Shiung; Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng, Post passivation metal scheme for high-performance integrated circuit devices.
  68. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation method for semiconductor chip or wafer.
  69. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation structure for semiconductor chip or wafer.
  70. Lin, Mou-Shiung; Lee, Jin-Yuan, Semiconductor chip structure.
  71. Lin, Mou-Shiung; Yen, Huei-Mei; Lo, Hsin-Jung; Chou, Chiu-Ming; Chen, Ke-Hung, Semiconductor chip with a bonding pad having contact and test areas.
  72. Lee, Wen-Chieh; Lin, Mou-Shiung; Chou, Chien-Kang; Liu, Yi-Cheng; Chou, Chiu-Ming; Lee, Jin-Yuan, Semiconductor chip with coil element over passivation layer.
  73. Lee, Wen-Chieh; Lin, Mou-Shiung; Chou, Chien-Kang; Liu, Yi-Cheng; Chou, Chiu-Ming; Lee, Jin-Yuan, Semiconductor chip with coil element over passivation layer.
  74. Chou, Chiu-Ming; Chou, Chien-Kang; Lin, Ching-San; Lin, Mou-Shiung, Semiconductor chip with passivation layer comprising metal interconnect and contact pads.
  75. Lin, Mou-Shiung; Lo, Hsin-Jung; Chou, Chien-Kang; Chou, Chiu-Ming; Lin, Ching-San, Semiconductor chip with post-passivation scheme formed over passivation layer.
  76. Lin, Mou-Shiung; Lo, Hsin-Jung; Chou, Chien-Kang; Chou, Chiu-Ming; Lin, Ching-San, Semiconductor chip with post-passivation scheme formed over passivation layer.
  77. Lin, Mou Shiung; Ting, Tah Kang Joseph, Semiconductor chip with redistribution metal layer.
  78. Katagiri, Mitsuaki; Usami, Masami; Ujiie, Kenji, Semiconductor device.
  79. Saijo,Kinji; Ohsawa,Shingji; Okamoto,Hiroaki; Yoshida,Kazuo; Suga,Tadatomo, Semiconductor device and fabrication method therefor.
  80. Ohuchi, Shinji, Semiconductor device and manufacturing method thereof.
  81. Tsubosaki, Kunihiro, Semiconductor device and method for fabricating the semiconductor device.
  82. Kikuchi, Hidekazu, Semiconductor device and method for manufacturing.
  83. Park, Young-ju; Min, Jae-ho; Kim, Myeong-cheol; Kim, Dong-chan; Sim, Jae-hwang, Semiconductor devices having narrow conductive line patterns and related methods of forming such semiconductor devices.
  84. Lu, Fang; Salem, Ali, Semiconductor die with reduced bump-to-pad ratio.
  85. Hirayama, Takeshi, Semiconductor integrated circuit device, mounting board, and device and board assembly.
  86. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Semiconductor package with interconnect layers.
  87. Yang, Seung Taek; Park, Shin Young, Semiconductor package with pad parts electrically connected to bonding pads through re-distribution layers.
  88. Lin, Mou-Shiung; Lei, Ming-Ta; Lin, Chuen-Jye, Structure and manufacturing method of a chip scale package.
  89. Chou, Chiu-Ming; Lin, Mou-Shiung, Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures.
  90. Chia, Yong Poo; Boon, Suan Jeung; Low, Siu Waf; Neo, Yong Loo; Ser, Bok Leng, Super high density module with integrated wafer level packages.
  91. Chia, Yong Poo; Boon, Suan Jeung; Low, Siu Waf; Neo, Yong Loo; Ser, Bok Leng, Super high density module with integrated wafer level packages.
  92. Chia,Yong Poo; Boon,Suan Jeung; Low,Siu Waf; Neo,Yong Loo; Ser,Bok Leng, Super high density module with integrated wafer level packages.
  93. Chia, Yong Poo; Boon, Suan Jeung; Low, Siu Waf; Neo, Yong Loo; Ser, Bok Leng, Super high-density module with integrated wafer level packages.
  94. Chia, Yong Poo; Boon, Suan Jeung; Low, Siu Waf; Neo, Yong Loo; Ser, Bok Leng, Super high-density module with integrated wafer level packages.
  95. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  96. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  97. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  98. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  99. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  100. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  101. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  102. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  103. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  104. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  105. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  106. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  107. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  108. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  109. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  110. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  111. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  112. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  113. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  114. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  115. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  116. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  117. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  118. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  119. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  120. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  121. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  122. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  123. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  124. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  125. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
  126. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Top layers of metal for integrated circuits.
  127. Lin, Mou-Shiung, Wirebond over post passivation thick metal.
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