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Method of wafer smoothing for bonding using chemo-mechanical polishing (CMP) 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • B24B-001/00
출원번호 US-0675841 (2000-09-29)
발명자 / 주소
  • Donald F. Canaperi
  • Jack Oon Chu
  • Guy M. Cohen
  • Lijuan Huang
  • John Albrecht Ott
  • Michael F. Lofaro
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Scully, Scott, Murphy & Presser
인용정보 피인용 횟수 : 39  인용 특허 : 9

초록

A method and apparatus is described incorporating a semiconductor substrate, a CMP tool, a brush cleaning tool, and a chemical wafer cleaning tool. The CMP is performed with a down force of 1 psi, a backside air pressure of 0.5 psi, a platen speed of 50 rpm, a crarrier speed of 30 rpm and a slurry f

대표청구항

1. An apparatus for polishing and smoothing a wafer surface suitable for performing wafer to wafer bonding comprising:a semiconductor substrate, a first layer of material formed on said substrate, a CMP tool, a brush cleaning tool, a chemical wafer cleaning tool, and a wafer bonding tool.

이 특허에 인용된 특허 (9)

  1. Nakashiba Masamichi,JPX ; Kimura Norio,JPX ; Watanabe Isamu,JPX ; Yoshida Kaori,JPX, Apparatus for and method for polishing workpiece.
  2. Shamouilian Sam ; Shendon Norm, Carrier head with a layer of conformable material for a chemical mechanical polishing system.
  3. Chen Lai-Juh,TWX, Chemical-mechanical polish (CMP) pad conditioner.
  4. Fitzgerald Eugene A., Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization.
  5. Mack Kenneth D., Method and apparatus for chemical-mechanical polishing.
  6. Koos Daniel A. ; Kim Sung C. ; Sandhu Gurtej S., Method of chemical mechanical polishing.
  7. Sadana Devendra Kumar ; Holland Orin Wayne, Method of forming buried oxide layers in silicon.
  8. Bruel Michel (Veurey FRX), Process for the production of thin semiconductor material films.
  9. Chamberlin Timothy S. ; Miller Matthew K. ; Walton Erick G., Slurry injection technique for chemical-mechanical polishing.

이 특허를 인용한 특허 (39)

  1. Gaudin, Gweltaz, 3D integrated heterostructures having low-temperature bonded interfaces with high bonding energy.
  2. Dinh-Ngoc, Charles; Ramanath, Srinivasan; Schulz, Eric M.; Wu, Jianhui; Puthanangady, Thomas; Vedantham, Ramanujam; Hwang, Taewook, Abrasive tool for use as a chemical mechanical planarization pad conditioner.
  3. Wu, Jianhui; Hall, Richard W. J.; Schulz, Eric M.; Ramanath, Srinivasan, Chemical mechanical polishing conditioner.
  4. Currie,Matthew T., Control of strain in device layers by prevention of relaxation.
  5. Currie,Matthew T., Control of strain in device layers by selective relaxation.
  6. Fitzgerald, Eugene A.; Pitera, Arthuer J., Coplanar integration of lattice-mismatched semiconductor with silicon via wafer bonding virtual substrates.
  7. Wu, Jianhui; Hwang, Taewook; Vedantham, Ramanujam; Dinh-Ngoc, Charles; Puthanangady, Thomas K.; Schulz, Eric M.; Ramanath, Srinivasan, Corrosion-resistant CMP conditioning tools and methods for making and using same.
  8. Wu,Kenneth C.; Fitzgerald,Eugene A.; Taraschi,Gianni; Borenstein,Jeffrey T., Etch stop layer system.
  9. Currie, Matthew T., Hybrid fin field-effect transistor structures and related methods.
  10. Gaudin, Gweltaz, Low-temperature bonding process.
  11. Maekawa, Kazuyoshi, Manufacturing method of back illumination CMOS image sensor device using wafer bonding.
  12. Maekawa, Kazuyoshi, Manufacturing method of back illumination CMOS image sensor device using wafer bonding.
  13. Ohnuma, Hideto; Shingu, Takashi; Kakehata, Tetsuya; Kuriki, Kazutaka; Yamazaki, Shunpei, Method for manufacturing SOI substrate.
  14. Akimoto, Kengo; Endo, Yuta, Method for manufacturing SOI substrate and method for manufacturing semiconductor device.
  15. Schwandner, Juergen; Koppert, Roland, Method for polishing a semiconductor wafer with a strained-relaxed Si1−xGex layer.
  16. Cheng,Zhiyuan; Fitzgerald,Eugene A.; Antoniadis,Dimitri A., Method of fabricating a semiconductor structure that includes transferring one or more material layers to a substrate and smoothing an exposed surface of at least one of the material layers.
  17. Jiang, Li; Li, Mingqi, Method of manufacturing a semiconductor device.
  18. Fitzgerald,Eugene; Currie,Matthew, Methods for fabricating strained layers on semiconductor substrates.
  19. Langdo, Thomas A.; Currie, Matthew T.; Hammond, Richard; Lochtefeld, Anthony J.; Fitzgerald, Eugene A., Methods for forming III-V semiconductor device structures.
  20. Langdo, Thomas A.; Currie, Matthew T.; Hammond, Richard; Lochtefeld, Anthony J.; Fitzgerald, Eugene A., Methods for forming strained-semiconductor-on-insulator device structures by mechanically inducing strain.
  21. Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Methods for forming strained-semiconductor-on-insulator device structures by use of cleave planes.
  22. Currie,Matthew T., Methods of forming hybrid fin field-effect transistor structures.
  23. Langdo, Thomas A.; Currie, Matthew T.; Hammond, Richard; Lochtefeld, Anthony J.; Fitzgerald, Eugene A., Methods of forming strained-semiconductor-on-insulator device structures.
  24. Lochtefeld,Anthony J.; Langdo,Thomas A.; Hammond,Richard; Currie,Matthew T.; Braithwaite,Glyn; Fitzgerald,Eugene A., Methods of forming strained-semiconductor-on-insulator finFET device structures.
  25. Martinez, Muriel; Metral, Frédéric; Reynaud, Patrick; Chahra, Zohra, Planarization of a heteroepitaxial layer.
  26. Schwandner, Juergen; Koppert, Roland, Polishing pad and method for polishing a semiconductor wafer.
  27. Guiot, Eric; Lallement, Fabrice, Process for fabricating a substrate comprising a deposited buried oxide layer.
  28. Cheng, Zhi-Yuan; Fitzgerald, Eugene A.; Antoniadis, Dimitri A.; Hoyt, Judy L., Process for producing semiconductor article using graded epitaxial growth.
  29. Cheng, Zhiyuan; Fitzgerald, Eugene A.; Antoniadis, Dimitri A., Semiconductor device structure.
  30. Westhoff, Richard; Yang, Vicky K.; Currie, Matthew T.; Vineis, Christopher; Leitz, Christopher, Semiconductor heterostructures having reduced dislocation pile-ups and related methods.
  31. Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained germanium-on-insulator device structures.
  32. Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained-semiconductor-on-insulator device structures.
  33. Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained-semiconductor-on-insulator device structures.
  34. Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained-semiconductor-on-insulator device structures with elevated source/drain regions.
  35. Langdo,Thomas A.; Currie,Matthew T.; Braithwaite,Glyn; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained-semiconductor-on-insulator finFET device structures.
  36. Cheng, Kangguo; Doris, Bruce B.; Hashemi, Pouya; Khakifirooz, Ali; Reznicek, Alexander, Type III-V and type IV semiconductor device formation.
  37. Cheng, Kangguo; Doris, Bruce B.; Hashemi, Pouya; Khakifirooz, Ali; Reznicek, Alexander, Type III-V and type IV semiconductor device formation.
  38. Yu,Lianzhong, Vibrating beam accelerometer.
  39. Yu, Lianzhong, Vibrating beam accelerometer two-wafer fabrication process.
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