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Semiconductor device and method for fabricating the same

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/72
출원번호 US-0527263 (2000-03-17)
우선권정보 KR-0009232 (1999-03-18)
발명자 / 주소
  • Eung Whan Min KR
출원인 / 주소
  • Hyundai Electronics Industries Co., Ltd. KR
대리인 / 주소
    Birch, Stewart, Kolasch & Birch, LLP
인용정보 피인용 횟수 : 56  인용 특허 : 5

초록

Semiconductor device and method for fabricating the same, in which a gate electrode is formed buried in a surface of a substrate, for improving device performance. The device includes device isolation layers each buried in a device isolation region of a semiconductor substrate for defining active re

대표청구항

1. A semiconductor device comprising:a semiconductor substrate having a gate trench therein, the gate trench having a first portion with a rectangular cross-section, and a second portion, formed beneath the first portion, having an elliptical cross-section and a width greater than a width of the fir

이 특허에 인용된 특허 (5)

  1. Dhong Sang H. (Mahopac NY) Hwang Wei (Armonk NY) Lu Nicky Chau-Chun (Yorktown Heights NY), Cross-point lightly-doped drain-source trench transistor and fabrication process therefor.
  2. Augustine Robert J. (Downers Grove IL) Shershen Mark (Downers Grove IL), Liquid heating and dispensing appliance and valve construction.
  3. Tseng Horng-Huei,TWX, Method for making improved shallow trench isolation with dielectric studs for semiconductor integrated circuits.
  4. Mitsumoto Hiroshi (Tokyo JPX), Semicondcutor device with high speed field effect transistor structure reducing concentrations of electric field near dr.
  5. Terasawa Yoshio,JPX ; Sekiya Takayuki,JPX, Semiconductor device and process for manufacturing the same.

이 특허를 인용한 특허 (56)

  1. Ananthan, Venkatesan; Tang, Sanh D., Dual work function recessed access device and methods of forming.
  2. Anathan, Venkatesan; Tang, Sanh D., Dual work function recessed access device and methods of forming.
  3. Gonzalez,Fernando, Electrical devices with multi-walled recesses.
  4. Haller, Gordon A.; Tang, Sanh D., Memory arrays and methods of fabricating memory arrays.
  5. Haller, Gordon A.; Tang, Sanh D., Memory arrays and methods of fabricating memory arrays.
  6. Lee, Pei-Ing; Cheng, Chien-Li; Lin, Shian-Jyh, Method for fabricating recessed gate MOS transistor device.
  7. Lee, Sang Don; Jeong, Jae Goan, Method for fabricating semiconductor device.
  8. Jung, Tae-Woo, Method for fabricating semiconductor device with recess gate.
  9. Kim, Jung Sam, Method for manufacturing a semiconductor device.
  10. Ikebuchi, Yoshinori, Method for manufacturing dynamic random access memory.
  11. Jang, Se-Aug; Cho, Heung-Jae; Kim, Tae-Yoon, Method for manufacturing recess gate in a semiconductor device.
  12. Jung,Tae O., Method for manufacturing semiconductor device.
  13. Jung, Tae Woo, Method of fabricating recess channel in semiconductor device.
  14. Lee, Sang Don; Chung, Sung Woong, Method of manufacturing semiconductor device with recess and Fin structure.
  15. Sandhu, Gurtej S.; Kiehlbauch, Mark, Methods of forming a plurality of transistor gates, and methods of forming a plurality of transistor gates having at least two different work functions.
  16. Hanson, Robert J.; Tang, Sanh D., Methods of forming field effect transistors on substrates.
  17. Hanson, Robert J.; Tang, Sanh D., Methods of forming field effect transistors on substrates.
  18. Hanson, Robert J.; Tang, Sanh D., Methods of forming field effect transistors on substrates.
  19. Kim, Young Pil; Parekh, Kunal R., Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates.
  20. Kim, Young Pil; Parekh, Kunal R., Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates.
  21. Gonzalez, Fernando, Methods of forming lines of capacitorless one transistor DRAM cells, methods of patterning substrates, and methods of forming two conductive lines.
  22. Parekh, Kunal R.; Mathew, Suraj J.; Trivedi, Jigish D.; Zahurak, John K.; Tang, Sanh D., Methods of forming recessed access devices associated with semiconductor constructions.
  23. Parekh, Kunal R.; Mathew, Suraj; Trivedi, Jigish D.; Zahurak, John K.; Tang, Sanh D., Methods of forming recessed access devices associated with semiconductor constructions.
  24. Tang, Sanh D.; Haller, Gordon A.; Doyle, Daniel H., Methods of making a semiconductor memory device.
  25. Yoon, Jae-man; Park, Dong-gun; Lee, Choong-Ho; Kim, Seong-Goo; Lee, Won-sok; Park, Seung-bae, Methods of manufacturing vertical channel semiconductor devices.
  26. Yoon, Jae-man; Park, Dong-gun; Lee, Choong-Ho; Kim, Seong-Goo; Lee, Won-sok; Park, Seung-bae, Methods of manufacturing vertical channel semiconductor devices.
  27. Gibbons, Jasper S.; Young, Darren V.; Parekh, Kunal R.; Smith, Casey, Recessed access devices and gate electrodes.
  28. Smith, Casey; Gibbons, Jasper S.; Parekh, Kunal R., Recessed antifuse structures and methods of making the same.
  29. Gibbons, Jasper S.; Young, Darren V.; Parekh, Kunal R.; Smith, Casey, Recessed memory cell access devices and gate electrodes.
  30. Tang, Sanh D.; Haller, Gordon A.; Brown, Kris K.; Allen, III, Tuman Earl, Semiconductor constructions and transistors, and methods of forming semiconductor constructions and transistors.
  31. Ohtani, Kinya, Semiconductor device.
  32. Park, Dong-Il; Kim, Ae-Gyeong; Kim, Jong-Sam; Uhm, Kyoung-Eun; Lee, Tae-Cheol; Jeong, Yong-Sang; Jeong, Jin-Ha, Semiconductor device.
  33. Hasunuma, Eiji, Semiconductor device and manufacture method therefor.
  34. Lee, Sang Don; Jeong, Jae Goan, Semiconductor device and method for fabricating the same.
  35. Juengling, Werner, Semiconductor device comprising a transistor gate having multiple vertically oriented sidewalls.
  36. Juengling, Werner, Semiconductor device comprising a transistor gate having multiple vertically oriented sidewalls.
  37. Juengling, Werner, Semiconductor device comprising a transistor gate having multiple vertically oriented sidewalls.
  38. Jang, Sung-Ho; Choi, Yong-Jin; Kang, Min-Sung; Lee, Kwang-Woo, Semiconductor device employing transistor having recessed channel region and method of fabricating the same.
  39. Yoo, Min Soo, Semiconductor device having a buried gate that can realize a reduction in gate-induced drain leakage (GIDL) and method for manufacturing the same.
  40. Yoo, Min Soo, Semiconductor device having a buried gate that can realize a reduction in gate-induced drain leakage (GIDL) and method for manufacturing the same.
  41. Chung, Sung Woong; Lee, Sang Don, Semiconductor device having a recess channel transistor.
  42. Lin, Jeng Ping; Lee, Pei Ing, Semiconductor device having a trench gate and method of fabricating the same.
  43. Baek, Seung Joo, Semiconductor device manufactured with a double shallow trench isolation process.
  44. Baek, Seung Joo, Semiconductor device manufactured with a double shallow trench isolation process.
  45. Lee, Sang Don, Semiconductor device with a surrounded channel transistor.
  46. Lee, Sang Don; Chung, Sung Woong, Semiconductor device with recess and fin structure.
  47. Kim, Yong-il; Cho, Min-Hee, Semiconductor devices having a recessed active edge.
  48. Yamada, Satoru; Oyu, Kiyonori; Kimura, Shinichiro, Semiconductor integrated circuit device and process for manufacturing the same.
  49. Gonzalez, Fernando, Transistor structures and integrated circuitry comprising an array of transistor structures.
  50. Tang, Sanh D.; Haller, Gordon; Brown, Kris K.; Allen, III, Tuman Earl, Transistors.
  51. Cho,Min Hee; Kim,Ji Young, Transistors including laterally extended active regions and methods of fabricating the same.
  52. Lee, Sung-Sam; Cho, Min-Hee, Transistors with laterally extended active regions and methods of fabricating same.
  53. Gajda, Mark A., Trench-gate semiconductor devices, and their manufacture.
  54. Gajda, Mark A., Trench-gate semiconductor devices, and their manufacture.
  55. Gonzalez,Fernando, Vertical transistor and method of making.
  56. Gonzalez, Fernando, Vertical transistors, electrical devices containing a vertical transistor, and computer systems containing a vertical transistor.
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