초록 ▼

An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a regular routing structure, and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns wi

An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a regular routing structure, and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive regular input signals, perform a logic operation, and generate regular output signals. The regular routing structure is coupled to the FGs and configured to receive the regular output signals, route signals within the first FPGA tile, and provide the regular input signals to the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the regular routing structure and configured to transfer signals from the regular routing structure to outside of the first FPGA tile.

대표청구항 ▼

1. An apparatus including a field programmable gate array (FPGA), the FPGA comprising:a first FPGA tile comprising: a plurality of functional groups (FGs) arranged in rows and columns, each of the FGs being configurable to receive regular input signals, perform a logic operation, and generate regula

1. An apparatus including a field programmable gate array (FPGA), the FPGA comprising:a first FPGA tile comprising: a plurality of functional groups (FGs) arranged in rows and columns, each of the FGs being configurable to receive regular input signals, perform a logic operation, and generate regular output signals; a regular routing structure coupled to the FGs and configurable to receive the regular output signals, route signals within the first FPGA tile, and provide the regular input signals to the FGs; a plurality of interface groups (IGs) surrounding the plurality of FGs such that one IG is positioned at each end of each row and column, each of the IGs being coupled to the regular routing structure and configurable to transfer signals from the regular routing structure to outside of the FPGA tile and each of the IGs having a plurality of input multiplexers configurable to select signals received from outside of the FPGA tile and provide signals to the regular routing structure inside the FPGA tile; and a plurality of input/output pads (I/Os) coupled to at least one of said input multiplexers of at least one of said IGs.