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Semiconductor catalytic layer and atomic layer deposition thereof 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/40
출원번호 US-0609013 (2000-06-29)
발명자 / 주소
  • Sergey D. Lopatin
  • Carl J. Galewski
출원인 / 주소
  • Advanced Micro Devices, Inc.
대리인 / 주소
    Mikio Ishimaru
인용정보 피인용 횟수 : 56  인용 특허 : 5

초록

A semiconductor and manufacturing method is provided for device interconnects with a catalytic layer of copper, palladium, nickel, cobalt, silver, or other catalytic material deposited in a atomic layer by atomic layer epitaxy on a barrier layer of tantalum, titanium, tungsten, their nitrides, or a

대표청구항

1. A semiconductor comprising:a semiconductor substrate; a dielectric layer formed on a region of the semiconductor substrate; an opening in the dielectric layer, the opening defined by walls of the dielectric layer and exposing a conductive area in the semiconductor; a barrier layer over the dielec

이 특허에 인용된 특허 (5)

  1. Ting Chiu H. (Saratoga CA) Paunovic Milan (Port Washington NY), Electroless deposition for IC fabrication.
  2. Simpson Cindy Reidsema, Interconnect structure in a semiconductor device and method of formation.
  3. Schmidbauer Sven,DEX ; Ruf Alexander,DEX ; Schnabel Florian ; Hoinkis Mark ; Weber Stefan, Method of making a microelectronic structure.
  4. Lukanc Todd P. ; Wang Fei ; Avanzino Steven C., Optimized trench/via profile for damascene filling.
  5. Dubin Valery M. (Cupertino CA) Schacham-Diamand Yosi (Ithaca NY) Zhao Bin (Irvine CA) Vasudev Prahalad K. (Austin TX) Ting Chiu H. (Saratoga CA), Use of cobalt tungsten phosphide as a barrier material for copper metallization.

이 특허를 인용한 특허 (56)

  1. Paik,Young J., Adjusting manufacturing process control parameter using updated process threshold derived from uncontrollable error.
  2. Tabatabaie, Kamal; Hallock, Robert B., Atomic layer deposition in the formation of gate structures for III-V semiconductor.
  3. Schwarm,Alexander T., Automated design and execution of experiments with integrated model creation for semiconductor manufacturing tools.
  4. Ivanov, Igor C., Barrier layer configurations and methods for processing microelectronic topographies having barrier layers.
  5. Van Norman, Staci A.; Aston, Victoria J.; Weimer, Alan W., Catalyst support structure, catalyst including the structure, reactor including a catalyst, and methods of forming same.
  6. Gordon, Roy Gerald; Kim, Hoon; Bhandari, Harish, Cobalt nitride layers for copper interconnects and methods for forming them.
  7. Arackaparambil,John F.; Chi,Tom; Chow,Billy; D'Souza,Patrick M.; Hawkins,Parris; Huang,Charles; Jensen,Jett; Krishnamurthy,Badri N.; Kulkarni,Pradeep M.; Kulkarni,Prakash M.; Lin,Wen Fong; Mohan,Shan, Computer integrated manufacturing techniques.
  8. Arackaparambil,John F.; Chi,Tom; Chow,Billy; D'Souza,Patrick M.; Hawkins,Parris; Huang,Charles; Jensen,Jett; Krishnamurthy,Badri N.; Kulkarni,Pradeep M.; Kulkarni,Prakash M.; Lin,Wen Fong; Mohan,Shan, Computer integrated manufacturing techniques.
  9. Raaijmakers,Ivo; Haukka,Suvi P.; Saanila,Yille A.; Soininen,Pekka J.; Elers,Kai Erik; Granneman,Ernst H. A., Conformal lining layers for damascene metallization.
  10. Liaw, Jhon Jhy; Hsieh, Sung-Chun; Lin, Wesley; Wu, Chii-Ming W; Tsui, Ren-Fen, Connection structure for semiconductor devices.
  11. Paik, Young Joseph, Control of chemical mechanical polishing pad conditioner directional velocity to improve pad life.
  12. Shanmugasundram, Arulkumar; Parikh, Suketu A., Copper wiring module control.
  13. Borthakur, Swarnal, Corrosion resistant via connections in semiconductor substrates and methods of making same.
  14. Derderian, Garo J.; Sandhu, Gurtej S., Deposition methods.
  15. Derderian,Garo J.; Sandhu,Gurtej S., Deposition methods.
  16. Sandhu,Gurtej S.; Derderian,Garo J.; Blalock,Guy T.; Gilton,Terry L., Deposition methods and apparatuses providing surface activation.
  17. Shanmugasundram, Arulkumar P.; Schwarm, Alexander T., Dynamic metrology schemes and sampling schemes for advanced process control in semiconductor processing.
  18. Shanmugasundram, Arulkumar P.; Schwarm, Alexander T., Dynamic metrology schemes and sampling schemes for advanced process control in semiconductor processing.
  19. Shanmugasundram, Arulkumar P.; Schwarm, Alexander T., Dynamic metrology schemes and sampling schemes for advanced process control in semiconductor processing.
  20. Paik, Young Jeen, Dynamic offset and feedback threshold.
  21. Chi, Yueh-Shian; Hawkins, Parris C M; Huang, Charles Q., Dynamic subject information generation in message services of distributed object systems.
  22. Chi,Yueh shian T.; Hawkins,Parris C. M.; Huang,Charles Q., Dynamic subject information generation in message services of distributed object systems in a semiconductor assembly line facility.
  23. Elkins, Patricia C.; Moore, John T.; Klein, Rita J., Electroless plating of metal caps for chalcogenide-based memory devices.
  24. Elkins,Patricia C.; Moore,John T.; Klein,Rita J., Electroless plating of metal caps for chalcogenide-based memory devices.
  25. Krishnamurthy,Badri N.; Hawkins,Parris C. M., Experiment management system, method and medium.
  26. Shanmugasundram, Arulkumar P.; Schwarm, Alexander T.; Prabhu, Gopalakrishna B., Feedback control of a chemical mechanical polishing device providing manipulation of removal rate profiles.
  27. Shanmugasundram,Arulkumar P.; Schwarm,Alexander T.; Prabhu,Gopalakrishna B., Feedback control of a chemical mechanical polishing device providing manipulation of removal rate profiles.
  28. Shanmugasundram, Arulkumar P.; Schwarm, Alexander T.; Iliopoulos, Ilias; Parkhomovsky, Alexander; Seamons, Martin J., Feedback control of plasma-enhanced chemical vapor deposition processes.
  29. Paik,Young Joseph, Feedforward and feedback control for conditioning of chemical mechanical polishing pad.
  30. Chi, Yuehshian T.; Hawkins, Parris C. M.; Jin, Qiaolin, Generic interface builder.
  31. Shanmugasundram,Arulkumar P.; Schwarm,Alexander T., Integrating tool, module, and fab level control.
  32. Reiss,Terry P.; Shanmugasundram,Arulkumar P.; Schwarm,Alexander T., Integration of fault detection with run-to-run control.
  33. Mercaldi,Garry A., Low selectivity deposition methods.
  34. Mercaldi,Garry A., Low selectivity deposition methods.
  35. Ivanov, Igor C.; Zhang, Weiguo; Kolics, Artur, Method for strengthening adhesion between dielectric layers formed adjacent to metal layers.
  36. Schwarm,Alexander T.; Shanmugasundram,Arulkumar P.; Pan,Rong; Hernandez,Manuel; Mohammad,Amna, Method of feedback control of sub-atmospheric chemical vapor deposition processes.
  37. Nopper, Markus; Preusse, Axel, Method of forming a metal layer over patterned dielectric by electroless deposition using a catalyst.
  38. Kokotov,Yuri; Entin,Efim; Seror,Jacques; Fisher,Yossi; Sarel,Shalomo; Shanmugasundram,Arulkumar P.; Schwarm,Alexander T.; Paik,Young Jeen, Method, system and medium for controlling manufacture process having multivariate input parameters.
  39. Al Bayati,Amir; Adibi,Babak; Foad,Majeed; Somekh,Sasson, Method, system and medium for controlling semiconductor wafer processes using critical dimension measurements.
  40. Shanmugasundram,Arulkumar P.; Armer,Helen; Schwarm,Alexander T., Method, system and medium for process control for the matching of tools, chambers and/or other semiconductor-related entities.
  41. Schwarm,Alexander T.; Shanmugasundram,Arulkumar P.; Seror,Jacques; Kokotov,Yuri; Entin,Efim, Method, system, and medium for handling misrepresentative metrology data within an advanced process control system.
  42. Akram, Salman; Wark, James M.; Hiatt, William Mark, Methods of forming interconnects and semiconductor structures.
  43. Akram, Salman; Wark, James M.; Hiatt, William M., Methods of forming interconnects in a semiconductor structure.
  44. Somekh, Sasson; Grunes, Howard E., Multi-tool control system, method and medium.
  45. Paik,Young J., Process control by distinguishing a white noise component of a process variance.
  46. Paik,Young Jeen, Process control by distinguishing a white noise component of a process variance.
  47. Padhi,Deenesh; Gandikota,Srinivas; Naik,Mehul; Parikh,Suketu A.; Dixit,Girish A., Selective metal encapsulation schemes.
  48. Akram, Salman; Wark, James M.; Hiatt, William M., Semiconductor device structures including nickel plated aluminum, copper, and tungsten structures.
  49. Akram, Salman; Wark, James M.; Hiatt, William Mark, Semiconductor devices comprising nickel- and copper-containing interconnects.
  50. Cabral, Jr., Cyril; Dubois, Geraud J. M.; Edelstein, Daniel C.; Nogami, Takeshi; Sanders, Daniel P., Semiconductor interconnect structure having enhanced performance and reliability.
  51. Cabral, Jr., Cyril; Dubois, Geraud Jean-Michel; Edelstein, Daniel C.; Nogami, Takeshi; Sanders, Daniel P., Semiconductor interconnect structure having enhanced performance and reliability.
  52. Farrar, Paul A., Structures and methods to enhance copper metallization.
  53. Ito, Junichi; Yabe, Atsushi; Sekiguchi, Junnosuke; Imori, Toru, Substrate and manufacturing method therefor.
  54. Schwarm,Alexander T., System, method, and medium for monitoring performance of an advanced process control system.
  55. Surana,Rahul; Zutshi,Ajoy, Technique for process-qualifying a semiconductor manufacturing tool using metrology data.
  56. Doan,Trung Tri, Variable temperature deposition methods.
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