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Protective layers prior to alternating layer deposition

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/4763
출원번호 US-0843518 (2001-04-26)
발명자 / 주소
  • Ivo Raaijmakers NL
  • Pekka T. Soininen FI
  • Ernst H. A. Granneman NL
  • Suvi P. Haukka FI
출원인 / 주소
  • ASM Microchemistry Oy FI
대리인 / 주소
    Knobbe, Martens, Olson & Bear LLP
인용정보 피인용 횟수 : 264  인용 특허 : 14

초록

Method and structures are provided for conformal lining of dual damascene structures in integrated circuits, and particularly of openings formed in porous materials. Trenches and contact vias are formed in insulating layers. The pores on the sidewalls of the trenches and vias are blocked, and then t

대표청구항

1. A damascene metallization process, comprising:forming a trench in a desired wiring pattern in a porous insulating layer above a semiconductor substrate; forming a contact via extending downwardly from a floor of the trench to expose at least part of an underlying conductive element; blocking pore

이 특허에 인용된 특허 (14)

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  3. Stumborg Michael F. ; Santiago Francisco ; Chu Tak Kin ; Boulais Kevin A., Electronic devices with strontium barrier film and process for making same.
  4. Naoki Komai JP; Shingo Kadomura JP; Mitsuru Taguchi JP; Akira Yoshio JP; Takaaki Miyamoto JP, Interconnection structure and fabrication process therefor.
  5. Nguyen Tue ; Hsu Sheng Teng, Low resistance contact between integrated circuit metal levels and method for same.
  6. Posa John G. (Lake Oswego OR), Method and apparatus for producing a constant flow, constant pressure chemical vapor deposition.
  7. Suntola Tuomo,FIX ; Lindfors Sven,FIX ; Soininen Pekka,FIX, Method and equipment for growing thin films.
  8. Kelly Michael A. (121 Erica Way Portola Valley CA 94028), Method for chemical vapor deposition under a single reactor vessel divided into separate reaction chambers each with its.
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  14. Izumi Hirohiko (Sagamihara JPX), .

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