$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Configurable computational unit embedded in a programmable device 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-019/177
출원번호 US-0751538 (2000-12-29)
발명자 / 주소
  • Brian C. Faith
  • Thomas Oelsner GB
  • Gary N. Lai
출원인 / 주소
  • QuickLogic Corporation
대리인 / 주소
    Skjerven Morrill LLP
인용정보 피인용 횟수 : 248  인용 특허 : 6

초록

A plurality of configurable computational units are embedded in a programmable device, such as a field programmable gate array. Each configurable computational unit includes an adder circuit that is switchably coupled to a multiplier circuit and an accumulator circuit. The configurable computational

대표청구항

1. A programmable logic device, comprising:a plurality of input/output cells; an array of macrocells; a plurality of routing resources that programmably couple said macrocells and said input/output cells; and at least one configurable computational unit programmably coupled to said routing resources

이 특허에 인용된 특허 (6)

  1. Killion Darryl, Apparatus for soccer training.
  2. Kaviani Alireza S.,CAXITX M5R 2R5 ; Brown Steven D.,CAXITX M4R 2A3, Computational field programmable architecture.
  3. Prasad Mohit K. ; Srinivas Hosahalli R., Digital signal processor architecture optimized for performing fast Fourier Transforms.
  4. Ireton Mark A., Execute unit configured to selectably interpret an operand as multiple operands or as a single operand.
  5. New Bernard J., Multiplier fabric for use in field programmable gate arrays.
  6. Kelley Brian Todd ; Johnson David Mark, Multiply and accumulate circuit.

이 특허를 인용한 특허 (248)

  1. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  2. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  3. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  4. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
  7. Langhammer, Martin; Nguyen, Triet M.; Lin, Yi-Wen, Adder-rounder circuitry for specialized processing block in programmable logic device.
  8. Langhammer, Martin, Angular range reduction in an integrated circuit device.
  9. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
  10. Mar, Monte, Apparatus and method for programmable power management in a programmable analog circuit block.
  11. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  12. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  13. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  14. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
  15. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  16. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  17. Simkins, James M.; Young, Steven P.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y., Applications of cascading DSP slices.
  18. Ching, Alvin Y.; Wong, Jennifer; New, Bernard J.; Simkins, James M.; Thendean, John M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra, Architectural floorplan for a digital signal processing circuit.
  19. Simkins,James M.; Young,Steven P.; Wong,Jennifer; New,Bernard J.; Ching,Alvin Y., Arithmetic circuit with multiplexed addend inputs.
  20. Wong, Anna Wing Wah; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Simkins, James M.; Vadi, Vasisht Mantra; Schultz, David P., Arithmetic logic unit circuit.
  21. Jones,Anthony Mark, Asynchronous communication among hardware object nodes in IC with receive and send ports protocol registers using temporary register bypass select for validity information.
  22. Sullam, Bert; Kutz, Harold; Mar, Monte; Thiagaragen, Eashwar; Williams, Timothy; Wright, David G., Autonomous control in a programmable system.
  23. Langhammer, Martin, Calculation of trigonometric functions in an integrated circuit device.
  24. Langhammer, Martin, Calculation of trigonometric functions in an integrated circuit device.
  25. Langhammer, Martin, Calculation of trigonometric functions in an integrated circuit device.
  26. Langhammer, Martin, Calculation of trigonometric functions in an integrated circuit device.
  27. Wright, David G.; Williams, Timothy J., Circuit and method for improving the accuracy of a crystal-less oscillator having dual-frequency modes.
  28. Vorbach, Martin; Münch, Robert, Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs.
  29. Synder, Warren; Sullam, Bert, Clock driven dynamic datapath chaining.
  30. Langhammer, Martin, Combined adder and pre-adder for high-radix multiplier circuit.
  31. Langhammer, Martin, Combined floating point adder and subtractor.
  32. Mauer, Volker, Combined interpolation and decimation filter for programmable logic device.
  33. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
  34. Langhammer, Martin, Computing floating-point polynomials in an integrated circuit device.
  35. Langhammer, Martin; Pasca, Bogdan, Computing floating-point polynomials in an integrated circuit device.
  36. Nemecek, Craig, Conditional branching in an in-circuit emulation system.
  37. Teig, Steven; Schmit, Herman; Huang, Randy Renfu, Configurable IC having a routing fabric with storage elements.
  38. Teig, Steven; Schmit, Herman; Huang, Randy Renfu, Configurable IC having a routing fabric with storage elements.
  39. Schmit, Herman; Redgrave, Jason, Configurable IC with large carry chains.
  40. Redgrave, Jason; Schmit, Herman; Teig, Steven; Hutchings, Brad L.; Huang, Randy R., Configurable IC'S with large carry chains.
  41. Schmit, Herman; Redgrave, Jason, Configurable IC's with large carry chains.
  42. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
  43. Vorbach, Martin; Nückel, Armin, Configurable logic integrated circuit having a multidimensional structure of configurable elements.
  44. Best, Andrew; Ogami, Kenneth; Zhaksilikov, Marat, Configuration of programmable IC design elements.
  45. Langhammer, Martin, Configuring a programmable integrated circuit device to perform matrix multiplication.
  46. Langhammer, Martin, Configuring floating point operations in a programmable device.
  47. Langhammer, Martin, Configuring floating point operations in a programmable logic device.
  48. Miller, Marc; Reaves, Jimmy Lee, Content addressable memory in integrated circuit.
  49. Redgrave, Jason; Voogel, Martin; Teig, Steven, Controllable storage elements for an IC.
  50. Redgrave, Jason; Voogel, Martin; Teig, Steven, Controllable storage elements for an IC.
  51. Leung, Wai-Bor; Lui, Henry Y., DSP block for implementing large multiplier on a programmable integrated circuit device.
  52. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
  53. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
  54. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
  55. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.
  56. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.
  57. Vorbach, Martin; Münch, Robert, Data processor having disabled cores.
  58. Mihal, Andrew C.; Teig, Steven, Detailed placement with search and repair.
  59. Jones, Anthony Mark, Development system for an integrated circuit having standardized hardware objects.
  60. Jones,Anthony Mark, Development system for an integrated circuit having standardized hardware objects.
  61. Vorbach, Martin, Device including a field having function cells and information providing cells controlled by the function cells.
  62. Langhammer,Martin; Starr,Gregory; Hwang,Chiao Kai, Devices and methods with programmable logic and digital signal processing regions.
  63. Langhammer,Martin; Starr,Gregory; Hwang,Chiao Kai, Devices and methods with programmable logic and digital signal processing regions.
  64. New, Bernard J.; Vadi, Vasisht Mantra; Wong, Jennifer; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Simkins, James M., Digital signal processing block having a wide multiplexer.
  65. Simkins, James M.; Ching, Alvin Y.; Thendean, John M.; Vadi, Vasisht M.; Poon, Chi Fung; Rab, Muhammad Asim, Digital signal processing block with preadder stage.
  66. Demirsoy, Suleyman Sirri; Yi, Hyun, Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering.
  67. Demirsoy, Suleyman Sirri; Yi, Hyun, Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering.
  68. Demirsoy, Suleyman; Yi, Hyun, Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering.
  69. Simkins, James M.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra, Digital signal processing circuit having a SIMD circuit.
  70. Vadi, Vasisht Mantra; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Simkins, James M., Digital signal processing circuit having a pattern circuit for determining termination conditions.
  71. Vadi, Vasisht Mantra; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Simkins, James M., Digital signal processing circuit having a pattern detector circuit.
  72. New, Bernard J.; Wong, Jennifer; Simkins, James M.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra, Digital signal processing circuit having a pattern detector circuit for convergent rounding.
  73. Simkins, James M.; Thendean, John M.; Vadi, Vasisht Mantra; New, Bernard J.; Wong, Jennifer; Wong, Anna Wing Wah; Ching, Alvin Y., Digital signal processing circuit having a pre-adder circuit.
  74. Thendean, John M.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Simkins, James M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra, Digital signal processing circuit having an adder circuit with carry-outs.
  75. Simkins, James M.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra, Digital signal processing circuit having input register blocks.
  76. Langhammer, Martin, Digital signal processing circuitry with redundancy and ability to support larger multipliers.
  77. Langhammer, Martin; Lin, Yi-Wen; Streicher, Keone, Digital signal processing circuitry with redundancy and bidirectional data paths.
  78. Simkins, James M.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra; Schultz, David P., Digital signal processing element having an arithmetic logic unit.
  79. Langhammer, Martin, Discrete Fourier Transform in an integrated circuit device.
  80. Langhammer, Martin, Double-clocked specialized processing block in an integrated circuit device.
  81. Synder, Warren; Sullam, Bert, Dynamically configurable and re-configurable data path.
  82. Nemecek, Craig; Roe, Steve, External interface for event architecture.
  83. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
  84. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  85. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  86. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  87. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  88. Minz, Deboleena; Digari, Kailash, Field programmable gate array.
  89. Pleis, Matthew A.; Ogami, Kenneth Y.; Zhaksilikov, Marat, Graphical user interface for dynamically reconfiguring a programmable device.
  90. Anderson, Doug, Graphical user interface with user-selectable list-box.
  91. Vorbach, Martin; May, Frank, Hardware definition method including determining whether to implement a function as hardware or software.
  92. Chou, Shin-I, High-rate interpolation or decimation filter in integrated circuit device.
  93. Esposito,Benjamin; Pelt,Robert L, Hybrid multipliers implemented using DSP circuitry and programmable logic circuitry.
  94. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.
  95. Jones,Anthony Mark, IC comprising network of microprocessors communicating data messages along asynchronous channel segments using ports including validity and accept signal registers and with split / join capability.
  96. Pugh, Daniel J.; Caldwell, Andrew, IC that efficiently replicates a function to save logic and routing resources.
  97. Langhammer, Martin, Implementing division in a programmable integrated circuit device.
  98. Langhammer, Martin, Implementing large multipliers in a programmable integrated circuit device.
  99. Langhammer, Martin, Implementing mixed-precision floating-point operations in a programmable integrated circuit device.
  100. Langhammer, Martin, Implementing multipliers in a programmable integrated circuit device.
  101. Nemecek, Craig; Roe, Steve, In-circuit emulator and pod synchronized boot.
  102. Furtek, Frederick Curtis; Master, Paul L.; Plunkett, Robert Thomas, Input/output controller node in an adaptable computing environment.
  103. Seguine, Dennis R., Input/output multiplexer bus.
  104. Sequine, Dennis R., Input/output multiplexer bus.
  105. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.
  106. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.
  107. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.
  108. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.
  109. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
  110. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
  111. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logical cell array and bus system.
  112. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  113. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  114. Simkins,James M.; Young,Steven P.; Wong,Jennifer; New,Bernard J.; Ching,Alvin Y., Mathematical circuit with dynamic rounding.
  115. Langhammer, Martin, Matrix decomposition in an integrated circuit device.
  116. Kurtz, Brian L., Matrix operations in an integrated circuit device.
  117. Langhammer, Martin, Matrix operations in an integrated circuit device.
  118. Verdoorn, David Joel; Woodward, Sandra S., Method and apparatus for debugging a chip.
  119. Caldwell, Andrew; Schmit, Herman; Teig, Steven, Method and apparatus for decomposing functions in a configurable IC.
  120. Pugh, Daniel J., Method and apparatus for performing two's complement multiplication.
  121. Moyal, Nathan; Stiff, Jonathon, Method and circuit for rapid alignment of signals.
  122. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.
  123. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
  124. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
  125. Tseng, Steven; Tsang, Chris, Method and system for decimating an indexed set of data elements.
  126. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  127. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  128. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  129. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  130. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  131. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  132. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  133. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  134. Mauer, Volker; Demirsoy, Suleyman Sirri, Method for configuring a finite impulse response filter in a programmable logic device.
  135. Vorbach, Martin, Method for debugging reconfigurable architectures.
  136. Vorbach, Martin, Method for debugging reconfigurable architectures.
  137. Vorbach, Martin; May, Frank; Nückel, Armin, Method for debugging reconfigurable architectures.
  138. Vorbach, Martin; Nückel, Armin, Method for interleaving a program over a plurality of cells.
  139. Perrin, Jon; Seguine, Dennis, Method for parameterizing a user module.
  140. Vorbach, Martin; Nückel, Armin; May, Frank; Weinhardt, Markus; Cardoso, Joao Manuel Paiva, Method for processing data.
  141. Vorbach, Martin; May, Frank; Nückel, Armin, Method for the translation of programs for reconfigurable architectures.
  142. Wendling, Xavier; Simkins, James M., Method of and circuit for implementing a filter in an integrated circuit.
  143. Vorbach, Martin; Munch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
  144. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
  145. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
  146. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
  147. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
  148. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
  149. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
  150. Snyder, Warren S.; Mar, Monte, Microcontroller programmable system on a chip.
  151. Snyder, Warren S.; Mar, Monte, Microcontroller programmable system on a chip.
  152. Snyder, Warren S.; Mar, Monte, Microcontroller programmable system on a chip.
  153. Snyder, Warren, Microcontroller programmable system on a chip with programmable interconnect.
  154. Snyder, Warren S, Microcontroller programmable system on a chip with programmable interconnect.
  155. McDonald, John; Pearson, Jon; Ogami, Kenneth; Anderson, Doug, Model for a hardware device-independent method of defining embedded firmware for programmable systems.
  156. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.
  157. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.
  158. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.
  159. Langhammer, Martin, Multi-operand floating point operations in a programmable integrated circuit device.
  160. Langhammer, Martin, Multiple-precision processing block in a programmable integrated circuit device.
  161. Choe, Kok Heng; Ngai, Tony K; Lui, Henry Y., Multiplier-accumulator circuitry and methods.
  162. Snyder, Warren, Noninterfering multiply-MAC (multiply accumulate) circuit.
  163. Langhammer, Martin, Normalization of floating point operations in a programmable integrated circuit device.
  164. Langhammer, Martin, Normalization of floating point operations in a programmable integrated circuit device.
  165. Kutz, Harold, Numerical band gap.
  166. Rohe, Andre; Teig, Steven; Schmit, Herman; Redgrave, Jason; Caldwell, Andrew, Operational time extension.
  167. Snyder, Warren S.; Mar, Monte, PSOC architecture.
  168. Snyder, Warren; Mar, Monte, PSOC architecture.
  169. Snyder, Warren S.; Mar, Monte, PSoC architecture.
  170. Snyder, Warren S.; Mar, Monte, PSoC architecture.
  171. Pugh, Daniel J.; Redgrave, Jason; Caldwell, Andrew, Performing mathematical and logical operations in multiple sub-cycles.
  172. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
  173. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
  174. Mauer, Volker; Langhammer, Martin, Pipelined systolic finite impulse response filter.
  175. Langhammer, Martin, Polynomial calculations optimized for programmable integrated circuit device structures.
  176. Ogami, Kenneth Y., Power management architecture, method and configuration system.
  177. Ogami, Kenneth Y., Power management architecture, method and configuration system.
  178. Vorbach, Martin; Münch, Robert, Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like).
  179. Scheuermann,W. James, Processing architecture for a reconfigurable arithmetic node.
  180. Vorbach, Martin, Processor arrangement on a chip including data processing, memory, and interface elements.
  181. Vorbach, Martin; Münch, Robert, Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units.
  182. Vorbach, Martin; Nückel, Armin, Processor chip including a plurality of cache elements connected to a plurality of processor cores.
  183. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
  184. Davidson, Allan T.; Singh, Satwant; Mann, Shari L., Programmable and fixed logic circuitry for high-speed interfaces.
  185. Langhammer, Martin, Programmable device using fixed and configurable logic to implement floating-point rounding.
  186. Langhammer, Martin, Programmable device using fixed and configurable logic to implement recursive trees.
  187. Simkins, James M.; Young, Steven P.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y., Programmable device with dynamic DSP architecture.
  188. Mauer, Volker; Langhammer, Martin, Programmable device with specialized multiplier blocks.
  189. Kanno,Shinichi; Hida,Toshikatsu, Programmable gate array apparatus and method for switching circuits.
  190. Kanno,Shinichi; Hida,Toshikatsu, Programmable gate array apparatus and method for switching circuits.
  191. Langhammer,Martin; Hwang,Chiao Kai; Starr,Gregory, Programmable logic device including multipliers and configurations thereof to reduce resource utilization.
  192. Langhammer,Martin; Hwang,Chiao Kai; Starr,Gregory, Programmable logic device including multipliers and configurations thereof to reduce resource utilization.
  193. Simkins,James M.; Young,Steven P.; Wong,Jennifer; New,Bernard J.; Ching,Alvin Y., Programmable logic device with cascading DSP slices.
  194. Simkins,James M.; Young,Steven P.; Wong,Jennifer; New,Bernard J.; Ching,Alvin Y., Programmable logic device with pipelined DSP slices.
  195. Snyder, Warren, Programmable microcontroller architecture.
  196. Snyder, Warren; Mar, Monte, Programmable microcontroller architecture(mixed analog/digital).
  197. Snyder, Warren; Mar, Monte, Programmable microcontroller architecture(mixed analog/digital).
  198. Dasari,Ajithkumar V.; Shiao,Wilma Waiman; Pagarani,Tarachand G., Programmable multiplexer.
  199. Thiagarajan, Eashwar; Sivadasan, Mohandas Palatholmana; Rohilla, Gajender; Kutz, Harold; Mar, Monte, Programmable sigma-delta analog-to-digital converter.
  200. Snyder, Warren; Maheshwari, Dinesh; Ogami, Kenneth; Hastings, Mark, Providing hardware independence to automate code generation of processing device firmware.
  201. Langhammer, Martin, QR decomposition in an integrated circuit device.
  202. Mauer, Volker, QR decomposition in an integrated circuit device.
  203. Vorbach, Martin, Reconfigurable elements.
  204. Vorbach, Martin, Reconfigurable elements.
  205. Vorbach, Martin; Baumgarte, Volker, Reconfigurable general purpose processor having time restricted configurations.
  206. Vorbach, Martin, Reconfigurable sequencer structure.
  207. Vorbach, Martin, Reconfigurable sequencer structure.
  208. Vorbach, Martin, Reconfigurable sequencer structure.
  209. Pleis, Matthew A.; Sullam, Bert; Lesher, Todd, Reconfigurable testing system and method.
  210. Vorbach, Martin; Bretz, Daniel, Router.
  211. Davidson, Allan T.; Singh, Satwant, Scalable device architecture for high-speed interfaces.
  212. Caldwell, Andrew; Teig, Steven, Sequential delay analysis by placement engines.
  213. Nemecek, Craig, Sleep and stall in an in-circuit emulation system.
  214. Langhammer, Martin; Dhanoa, Kulwinder, Solving linear matrices in an integrated circuit device.
  215. Langhammer, Martin, Specialized processing block for implementing floating-point multiplier with subnormal operation support.
  216. Xu, Lei; Mauer, Volker; Perry, Steven, Specialized processing block for programmable integrated circuit device.
  217. Langhammer, Martin; Lee, Kwan Yee Martin; Azgomi, Orang; Streicher, Keone; Lin, Yi-Wen, Specialized processing block for programmable logic device.
  218. Langhammer, Martin; Lee, Kwan Yee Martin; Azgomi, Orang; Streicher, Keone; Pelt, Robert L., Specialized processing block for programmable logic device.
  219. Langhammer, Martin; Lee, Kwan Yee Martin; Nguyen, Triet M.; Streicher, Keone; Azgomi, Orang, Specialized processing block for programmable logic device.
  220. Lee, Kwan Yee Martin; Langhammer, Martin; Lin, Yi-Wen; Nguyen, Triet M., Specialized processing block for programmable logic device.
  221. Lee, Kwan Yee Martin; Langhammer, Martin; Nguyen, Triet M.; Lin, Yi-Wen, Specialized processing block for programmable logic device.
  222. Langhammer, Martin, Specialized processing block with fixed- and floating-point structures.
  223. Master,Paul L.; Watson,John, Storage and delivery of device features.
  224. Ogami, Kenneth; Best, Andrew; Zhaksilikov, Marat, System and method for controlling a target device.
  225. Anderson, Douglas H.; Ogami, Kenneth Y., System and method for dynamically generating a configuration datasheet.
  226. Ogami, Kenneth Y.; Hood, Frederick R., System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit.
  227. Ogami, Kenneth Y.; Hood, III, Frederick R., System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit.
  228. Schmit, Herman; Caldwell, Andrew; Hutchings, Brad; Redgrave, Jason; Teig, Steven, System and method for providing a virtual memory architecture narrower and deeper than a physical memory architecture.
  229. Schmit, Herman; Teig, Steven; Hutchings, Brad, System and method for providing more logical memory ports than physical memory ports.
  230. Schmit, Herman; Teig, Steven; Hutchings, Brad, System and method for providing more logical memory ports than physical memory ports.
  231. Schmit, Herman; Pugh, Daniel J.; Teig, Steven, System and method of providing a memory hierarchy.
  232. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
  233. Sullam, Bert; Snyder, Warren; Mohammed, Haneef, System level interconnect with programmable switching.
  234. Sullam, Bert; Snyder, Warren; Mohammed, Haneef, System level interconnect with programmable switching.
  235. Jones, Anthony Mark; Wasson, Paul M., System of hardware objects.
  236. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
  237. Ogami, Kenneth Y.; Anderson, Doug; Pleis, Matthew; Hood, III, Frederick Redding, Techniques for generating microcontroller configuration information.
  238. Ogami, Kenneth Y.; Anderson, Doug; Pleis, Matthew; Hood, Rick, Techniques for generating microcontroller configuration information.
  239. Teig, Steven; Caldwell, Andrew, Timing operations in an IC with configurable circuits.
  240. Teig, Steven; Caldwell, Andrew, Timing operations in an IC with configurable circuits.
  241. Beard, Paul; Woodings, Ryan Winfield, Touch wake for electronic devices.
  242. Pugh, Daniel J.; Schmit, Herman; Redgrave, Jason; Caldwell, Andrew, Use of hybrid interconnect/logic circuits for multiplication.
  243. Bartz, Manfred; Zhaksilikov, Marat; Anderson, Doug, User interface for efficiently browsing an electronic document using data-driven tabs.
  244. Redgrave, Jason, User registers implemented with routing circuits in a configurable IC.
  245. Redgrave, Jason, Users registers implemented with routing circuits in a configurable IC.
  246. Hutchings, Brad, Variable width management for a memory of a configurable IC.
  247. Hutchings, Brad, Variable width writing to a memory of an IC.
  248. Sivadasan, Mohandas Palatholmana; Rohilla, Gajendar, Voltage controlled oscillator delay cell and method.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로