초록 ▼

An integrated circuit device including a FIFO and a clock generator having a pulse swallower. The pulse swallower eliminates pulses from a reference frequency signal, producing a primary digital transceiver clock signal having a frequency of chiprate(S)(n), which is used to clock a digital transceiv

An integrated circuit device including a FIFO and a clock generator having a pulse swallower. The pulse swallower eliminates pulses from a reference frequency signal, producing a primary digital transceiver clock signal having a frequency of chiprate(S)(n), which is used to clock a digital transceiver when the device is in a primary mode. A first clock divider divides the frequency of the primary digital transceiver clock signal to produce a FIFO output clock signal having a frequency of chiprate(S). The FIFO has a data bus input for coupling to a data output, for example from an analog transceiver. The FIFO also has an external clock input for coupling to a clock output, for example from the analog transceiver. The external clock signal clocks the data into the FIFO asynchronous with the primary digital transceiver clock signal at a frequency of chiprate(S). The internal clock signal clocks the data out of the FIFO, synchronous with the primary digital transceiver clock signal at a frequency of chiprate(S). When in a secondary power savings mode, the pulse swallower produces an output signal having a frequency of chiprate which is used to maintain CDMA network time, permitting the analog transceiver to be powered down during the secondary mode. In another embodiment of the invention, the external clock signal from the analog transceiver having a frequency of chiprate(S) is multiplied by (n) to produce the primary digital transceiver clock signal.

대표청구항 ▼

1. A method for generating a plurality of clock signals from a single reference frequency signal and synchronizing data signals with one of the generated clock signals, comprising:processing a reference frequency signal to produce a clock signal for use by a transceiver in a spread spectrum communic

1. A method for generating a plurality of clock signals from a single reference frequency signal and synchronizing data signals with one of the generated clock signals, comprising:processing a reference frequency signal to produce a clock signal for use by a transceiver in a spread spectrum communications apparatus; dividing the clock signal by n to produce a FIFO output clock signal; clocking the data signals into a FIFO with an external clock signal, the external clock signal being asynchronous with the FIFO output clock signal; and clocking the data signals out of the FIFO with the FIFO output clock signal.