이 특허를 인용한 특허 (139)

1. Gunn, III,Lawrence C.; Li,Bing; Pinguet,Thierry J.; Press,David L. R.; Rattier,Maxime Jean, Active waveguides for optoelectronic devices.

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2. Gunn, III,Lawrence C.; Li,Bing; Pinguet,Thierry J.; Press,David; Rattier,Maxime Jean, Active waveguides for optoelectronic devices.

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3. Gunn, III,Lawrence C.; Li,Bing; Pinguet,Thierry J.; Press,David; Rattier,Maxime Jean, Active waveguides for optoelectronic devices.

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4. Chen, Xiangdong; Dyer, Thomas W.; Settlemyer, Kenneth; Yang, Haining S., CMOS devices with stressed channel regions, and methods for fabricating the same.

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5. Zhu, Huilong; Yang, Baewon, CMOS structures and methods for improving yield.

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6. Zhu, Huilong; Yang, Daewon, CMOS structures and methods for improving yield.

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7. Zhu, Huilong; Yang, Daewon, CMOS structures and methods using self-aligned dual stressed layers.

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8. Cheng, Cheng-Wei; Li, Ning; Sadana, Devendra K.; Shiu, Kuen-Ting, Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxial semiconductor material formed using lateral overgrowth.

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9. Cheng, Cheng-Wei; Li, Ning; Sadana, Devendra K.; Shiu, Kuen-Ting, Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxial semiconductor material formed using lateral overgrowth.

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10. Cheng, Cheng-Wei; Li, Ning; Sadana, Devendra K.; Shiu, Kuen-Ting, Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxial semiconductor material formed using lateral overgrowth.

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11. Cheng, Cheng-Wei; Li, Ning; Sadana, Devendra K.; Shiu, Kuen-Ting, Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxially formed material.

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12. Cheng, Cheng-Wei; Li, Ning; Sadana, Devendra K.; Shiu, Kuen-Ting, Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxially formed material.

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13. Zhu,Huilong; Doris,Bruce B.; Chen,Huajie, Dislocation free stressed channels in bulk silicon and SOI CMOS devices by gate stress engineering.

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14. Fang, Sunfei; Kim, Jun Jung; Luo, Zhijiong; Ng, Hung Y.; Rovedo, Nivo; Teh, Young Way, Dual stress memory technique method and related structure.

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15. Chidambarrao,Dureseti; Dokumaci,Omer H.; Doris,Bruce B.; Gluschenkov,Oleg; Zhu,Huilong, Dual stressed SOI substrates.

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16. Chidambarrao,Dureseti; Doris,Bruce B.; Gluschenkov,Oleg; Dokumaci,Omer H.; Zhu,Huilong, Dual stressed SOI substrates.

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17. Iwashita, Setsuya; Higuchi, Takamitsu; Miyazawa, Hiromu, Electronic device and electronic apparatus.

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18. Chidambarrao,Dureseti, Enhanced PFET using shear stress.

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19. Zhu, Huilong; Luo, Zhijiong, FinFET structure with multiply stressed gate electrode.

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20. Chidambarrao, Dureseti, Gate electrode stress control for finFET performance enhancement.

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21. Mule′, Tony; Patel, Chirag; Meindl, James D.; Gaylord, Thomas K.; Glytsis, Elias N.; Martin, Kevin P.; Schultz, Stephen M.; Bakir, Muhannad; Reed, Hollie; Kohl, Paul, Guided-wave optical interconnections embedded within a microelectronic wafer-level batch package.

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22. Doris, Bruce B.; Gluschenkov, Oleg G.; Zhu, Huilong, High mobility CMOS circuits.

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23. Doris,Bruce B.; Gluschenkov,Oleg G.; Zhu,Huilong, High mobility CMOS circuits.

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24. Doris,Bruce B.; Gluschenkov,Oleg G.; Zhu,Huilong, High mobility CMOS circuits.

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25. Doris,Bruce B.; Chidambarrao,Dureseti; Ku,Suk Hoon, High performance CMOS device structures and method of manufacture.

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26. Doris,Bruce B.; Chidambarrao,Dureseti; Ku,Suk Hoon, High performance CMOS device structures and method of manufacture.

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27. Doris, Bruce B; Gluschenkov, Oleg G, High performance strained CMOS devices.

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28. Doris,Bruce B.; Gluschenkov,Oleg G., High performance strained CMOS devices.

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29. Chidambarrao, Dureseti; Donaton, Ricardo A.; Henson, William K.; Rim, Kern, High performance stress-enhance MOSFET and method of manufacture.

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30. Chidambarrao, Dureseti; Donaton, Ricardo A.; Henson, William K.; Rim, Kern, High performance stress-enhance MOSFET and method of manufacture.

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31. Chidambarrao, Dureseti; Donaton, Ricardo A.; Henson, William K.; Rim, Kern, High performance stress-enhance MOSFET and method of manufacture.

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32. Chen, Huajie; Chidambarrao, Dureseti; Dokumaci, Omer H., High performance stress-enhanced MOSFETS using Si:C and SiGe epitaxial source/drain and method of manufacture.

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33. Chen, Huajie; Chidambarrao, Dureseti; Dokumaci, Omer H., High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture.

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34. Chen, Huajie; Chidambarrao, Dureseti; Dokumaci, Omer H., High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture.

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35. Chen, Huajie; Chidambarrao, Dureseti; Dokumaci, Omer H., High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture.

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36. Chen,Huajie; Chidambarrao,Dureseti; Dokumaci,Omer H, High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture.

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37. Doris, Bruce B.; Guarini, Kathryn W.; Ieong, Meikei; Narasimha, Shreesh; Rim, Kern; Sleight, Jeffrey W.; Yang, Min, High-performance CMOS SOI devices on hybrid crystal-oriented substrates.

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38. Doris,Bruce B.; Guarini,Kathryn W.; Ieong,Meikei; Narasimha,Shreesh; Rim,Kern; Sleight,Jeffrey W.; Yang,Min, High-performance CMOS devices on hybrid crystal oriented substrates.

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39. Montgomery, Robert Keith; Ghiron, Margaret; Gothoskar, Prakash; Patel, Vipulkumar; Shastri, Kalpendu; Pathak, Soham; Yanushefski, Katherine A., High-speed silicon-based electro-optic modulator.

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40. Zhu,Huilong; Oldiges,Philip J.; Doris,Bruce B.; Wang,Xinlin; Gluschenkov,Oleg; Chen,Huajie; Zhang,Ying, Hybrid SOI-bulk semiconductor transistors.

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41. Zhu, Huilong; Oldiges, Philip J.; Doris, Bruce B.; Wang, Xinlin; Gluschenkov, Oleg; Chen, Huajie; Zhang, Ying, Hybrid SOI/bulk semiconductor transistors.

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42. Cheng, Cheng-Wei; Li, Ning; Sadana, Devendra K.; Shiu, Kuen-Ting, III-V photonic integrated circuits on silicon substrate.

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43. Chidambarrao, Dureseti; Dokumaci, Omer H., MOSFET performance improvement using deformation in SOI structure.

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44. Chidambarrao, Dureseti; Dokumaci, Omer H., MOSFET performance improvement using deformation in SOI structure.

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45. Yang, Haining S.; Zhu, Huilong, Method and apparatus for increase strain effect in a transistor channel.

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46. Yang,Haining S.; Zhu,Huilong, Method and apparatus for increase strain effect in a transistor channel.

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47. Yang,Haining S.; Zhu,Huilong, Method and apparatus to increase strain effect in a transistor channel.

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48. Yang,Haining S.; Zhu,Huilong, Method and structure for controlling stress in a transistor channel.

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49. Steegen, An L.; Yang, Haining S.; Zhang, Ying, Method and structure for forming strained SI for CMOS devices.

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50. Steegen,An L; Yang,Haining S.; Zhang,Ying, Method and structure for forming strained SI for CMOS devices.

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51. Steegen, An L.; Yang, Haining S.; Zhang, Ying, Method and structure for forming strained Si for CMOS devices.

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52. Steegen,An L.; Yang,Haining S.; Zhang,Ying, Method and structure for forming strained Si for CMOS devices.

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53. Yang, Haining S.; Lim, Eng Hua, Method and structure for forming strained devices.

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54. Chidambarrao, Dureseti; Dokumaci, Omer H., Method and structure for improved MOSFETs using poly/silicide gate height control.

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55. Chidambarrao,Dureseti; Dokumaci,Omer H., Method and structure for improved MOSFETs using poly/silicide gate height control.

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56. Chidambarrao, Dureseti; Greene, Brian J., Method and structure for improving device performance variation in dual stress liner technology.

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57. Chidambarrao,Dureseti; Greene,Brian J., Method and structure for improving device performance variation in dual stress liner technology.

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58. Chidambarrao,Dureseti; Dokumaci,Omer H., Method for reduced N+ diffusion in strained Si on SiGe substrate.

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59. Chidambarrao,Dureseti; Dokumaci,Omer H., Method for reduced N+ diffusion in strained Si on SiGe substrate.

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60. Chidambarrao,Dureseti; Dokumaci,Omer H., Method for reduced N+ diffusion in strained Si on SiGe substrate.

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61. Belyansky,Michael P.; Doris,Bruce B.; Gluschenkov,Oleg, Method of fabricating mobility enhanced CMOS devices.

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62. Chen, Huajie; Chidambarrao, Dureseti; Holt, Judson R.; Ouyang, Qiqing C.; Panda, Siddhartha, Method of forming a cross-section hourglass shaped channel region for charge carrier mobility modification.

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63. Chen,Xiaomeng; Jeng,Shwu Jen; Kim,Byeong Y.; Nayfeh,Hasan M., Method of making a semiconductor structure.

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64. Cheng,Kangguo; Chidambarrao,Dureseti, Method of manufacturing a strained silicon on a SiGe on SOI substrate.

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65. Chidambarrao,Dureseti; Dokumaci,Omer H., Method of manufacturing strained dislocation-free channels for CMOS.

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66. Yang, Haining S.; Panda, Siddhartha, Method to increase strain enhancement with spacerless FET and dual liner process.

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67. Guarin, Fernando; Hostetter, Jr., J. Edwin; Rauch, III, Stewart E.; Wang, Ping-Chuan; Yang, Zhijian J., Methodology for recovery of hot carrier induced degradation in bipolar devices.

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68. Arena, Chantal, Methods and structures for bonding elements.

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69. Belyansky, Michael P.; Doris, Bruce B.; Gluschenkov, Oleg G., Mobility enhanced CMOS devices.

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70. Adam, Thomas N.; Chidambarrao, Dureseti, Mobility enhancement in SiGe heterojunction bipolar transistors.

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71. Chidambarrao,Dureseti; Dokumaci,Omer H.; Gluschenkov,Oleg G., NFETs using gate induced stress modulation.

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72. Gibson, Gary, Optical devices.

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73. Block,Bruce A.; Barnett,Brandon C.; Davids,Paul, Optical waveguide devices having adjustable waveguide cladding.

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74. Talin,Albert Alec; Voight,Steven A., Optical waveguide structure and method for fabricating the same.

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75. Mule′, Tony; Meindl, James D.; Gaylord, Thomas K.; Glytsis, Elias N.; Kohl, Paul, Optical waveguides with embedded air-gap cladding layer and methods of fabrication thereof.

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76. Cheng, Kangguo; Divakaruni, Ramachandra, Patterned strained semiconductor substrate and device.

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77. Cheng, Kangguo; Divakaruni, Ramachandra, Patterned strained semiconductor substrate and device.

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78. Cheng, Kangguo; Divakaruni, Ramachandra, Patterned strained semiconductor substrate and device.

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79. Cheng,Kangguo; Divakaruni,Ramachandra, Patterned strained semiconductor substrate and device.

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80. Zhu,Huilong; Doris,Bruce B.; Mocuta,Dan M., Protecting silicon germanium sidewall with silicon for strained silicon/silicon mosfets.

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81. Chidambarrao, Dureseti; Mocuta, Anda C.; Mocuta, Dan M.; Radens, Carl, Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain.

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82. Chidambarrao, Dureseti; Mocuta, Anda C.; Mocuta, Dan M.; Radens, Carl, Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain.

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83. Beintner,Jochen; Bronner,Gary B.; Divakaruni,Ramachandra; Kim,Byeong Y., Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI structure with elevated source/drain.

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84. Chidambarrao,Dureseti, Rotational shear stress for charge carrier mobility modification.

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85. Chidambarrao,Dureseti, Rotational shear stress for charge carrier mobility modification.

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86. Deshpande,Sadanand V.; Doris,Bruce B.; Rausch,Werner A.; Slinkman,James A., STI stress modification by nitrogen plasma treatment for improving performance in small width devices.

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87. Chen, Xiangdong; Yang, Haining S., Semiconductor device structure having enhanced performance FET device.

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88. Arnold, John C.; Chidambarrao, Dureseti; Li, Ying; Malik, Rajeev; Narasimha, Shreesh; Panda, Siddhartha; Tessier, Brian L.; Wise, Richard, Semiconductor device structure having low and high performance devices of same conductive type on same substrate.

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89. Langer,Eckhard; Zschech,Ehrenfried, Semiconductor structure comprising a stress sensitive element and method of measuring a stress in a semiconductor structure.

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90. Chen, Xiaomeng; Jeng, Shwu-Jen; Kim, Byeong Y.; Nayfeh, Hasan M., Semiconductor structure having undercut-gate-oxide gate stack enclosed by protective barrier material.

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91. Zhu, Huilong; Greene, Brian J.; Chidambarrao, Dureseti; Freeman, Gregory G., Semiconductor-on-insulator structures including a trench containing an insulator stressor plug and method of fabricating same.

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92. Chidambarrao, Dureseti; Dokumaci, Omer H.; Rengarajan, Rajesh; Steegen, An L., Silicide proximity structures for CMOS device performance improvements.

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93. Chidambarrao, Dureseti; Dokumaci, Omer H.; Gluschenkov, Oleg, Silicon device on SI:C-OI and SGOI and method of manufacture.

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94. Chidambarrao, Duresti; Dokumaci, Omer H.; Gluschenkov, Oleg G., Silicon device on Si: C-oi and Sgoi and method of manufacture.

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95. Chidambarrao, Dureseti; Dokumaci, Omer H.; Gluschenkov, Oleg G., Silicon device on Si:C SOI and SiGe and method of manufacture.

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96. Chidambarrao, Dureseti; Dokumaci, Omer H.; Gluschenkov, Oleg G., Silicon device on Si:C-OI and SGOI and method of manufacture.

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97. Chidambarrao,Dureseti; Dokumaci,Omer H.; Gluschenkov,Oleg G., Silicon device on Si:C-OI and SGOI and method of manufacture.

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98. Ajmera, Atul C.; Baiocco, Christopher V.; Chen, Xiangdong; Gao, Wenzhi; Teh, Young Way, Spacer and process to enhance the strain in the channel with stress liner.

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99. de Souza, Joel P.; Hamaguchi, Masafumi; Ozcan, Ahmet S.; Sadana, Devendra K.; Saenger, Katherine L.; Wall, Donald R., Strain preserving ion implantation methods.

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100. Chan, Kevin K.; Chu, Jack O.; Rim, Kern; Shi, Leathen, Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI).

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101. Chan,Kevin K.; Chan,Jack Q; Rim,Kern; Shi,Leathen, Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI).

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102. Chan,Kevin K.; Chu,Jack O.; Rim,Kern; Shi,Leathen, Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI).

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103. Chan,Kevin K.; Chu,Jack O.; Rim,Kern; Shi,Leathen, Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI).

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104. Chidambarrao, Dureseti; Dokumaci, Omer H.; Gluschenkov, Oleg G.; Zhu, Huilong, Strained Si on multiple materials for bulk or SOI substrates.

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105. Chidambarrao,Dureseti; Dokumaci,Omer H.; Gluschenkov,Oleg G.; Zhu,Huilong, Strained Si on multiple materials for bulk or SOI substrates.

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106. Chidambarrao,Dureseti; Dokumaci,Omer H., Strained dislocation-free channels for CMOS and method of manufacture.

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107. Doris,Bruce B.; Chidambarrao,Dureseti; Ieong,MeiKei; Mandelman,Jack A., Strained finFET CMOS device structures.

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108. Chidambarrao,Dureseti; Dokumaci,Omer H.; Gluschenkov,Oleg G., Strained finFETs and method of manufacture.

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109. Cheng,Kangguo; Chidambarrao,Dureseti, Strained silicon on a SiGe on SOI substrate.

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110. Chidambarrao, Dureseti; Dokumaci, Omer H., Strained silicon on relaxed sige film with uniform misfit dislocation density.

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111. Bryant, Andres; Ouyang, Qiqing; Rim, Kern, Strained-silicon CMOS device and method.

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112. Bryant,Andres; Ouyang,Qiqing; Rim,Kern, Strained-silicon CMOS device and method.

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113. Chidambarrao, Dureseti; Henson, William K.; Rim, Kern; Wille, William C., Stress engineering using dual pad nitride with selective SOI device architecture.

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114. Chidambarrao,Dureseti; Henson,William K.; Rim,Kern; Wille,William C., Stress engineering using dual pad nitride with selective SOI device architecture.

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115. Zhu, Huilong; Wang, Jing, Stress-generating shallow trench isolation structure having dual composition.

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116. Zhu, Huilong; Wang, Jing, Stress-generating shallow trench isolation structure having dual composition.

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117. Zhu, Huilong; Wang, Jing, Stress-generating shallow trench isolation structure having dual composition.

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118. Zhu, Huilong; Greene, Brian J.; Chidambarrao, Dureseti; Freeman, Gregory G., Stress-generating structure for semiconductor-on-insulator devices.

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119. Zhu, Huilong; Greene, Brian J.; Chidambarrao, Dureseti; Freeman, Gregory G., Stress-generating structure for semiconductor-on-insulator devices.

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120. Doris,Bruce B.; Belyansky,Michael P.; Boyd,Diane C.; Chidambarrao,Dureseti; Gluschenkov,Oleg, Stressed semiconductor device structures having granular semiconductor material.

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121. Doris,Bruce B; Belyansky,Michael P; Boyd,Diane C; Chidambarrao,Dureseti; Gluschenkov,Oleg, Stressed semiconductor device structures having granular semiconductor material.

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122. Zhu,Huilong; Doris,Bruce B.; Oldiges,Philip J.; Ieong,Meikei; Yang,Min; Chen,Huajie, Structure and method for manufacturing planar strained Si/SiGe substrate with multiple orientations and different stress levels.

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123. Zhu,Huilong; Doris,Bruce B., Structure and method for manufacturing strained FINFET.

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124. Zhu,Huilong; Doris,Bruce B., Structure and method for manufacturing strained FINFET.

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125. Chan,Victor W. C.; Lee,Yong M.; Yang,Haining, Structure and method of applying stresses to PFET and NFET transistor channels for improved performance.

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126. Cabral, Jr.,Cyril; Doris,Bruce B.; Kanarsky,Thomas S.; Liu,Xiao H.; Zhu,Huilong, Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification.

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127. Yang,Haining S.; Zhu,Huilong, Structure and method to induce strain in a semiconductor device channel with stressed film under the gate.

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128. Chen,Xiangdong; Yang,Haining S., Structure and method to optimize strain in CMOSFETs.

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129. Yang, Haining; Li, Wai-Kin, Structure and method to use low k stress liner to reduce parasitic capacitance.

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130. Cheng,Kangguo; Chidambarrao,Dureseti; Divakaruni,Rama; Gluschenkov,Oleg G., Structure of vertical strained silicon devices.

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131. Zhu, Huilong; Bedell, Steven W.; Doris, Bruce B.; Zhang, Ying, Structures and methods for making strained MOSFETs.

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132. Zhu,Hiulong; Bedell,Steven W.; Doris,Bruce B.; Zhang,Ying, Structures and methods for making strained MOSFETs.

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133. Zhu,Huilong; Doris,Bruce B.; Chen,Huajie, Structures and methods for manufacturing of dislocation free stressed channels in bulk silicon and SOI CMOS devices by gate stress engineering with SiGe and/or Si:C.

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134. Zhu, Huilong; Doris, Bruce B.; Chen, Huajie, Structures and methods for manufacturing of dislocation free stressed channels in bulk silicon and SOI MOS devices by gate stress engineering with SiGe and/or Si:C.

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135. Zhu,Huilong, Structures and methods for manufacturing p-type MOSFET with graded embedded silicon-germanium source-drain and/or extension.

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136. Gothoskar, Prakash; Ghiron, Margaret; Montgomery, Robert Keith; Patel, Vipulkumar; Shastri, Kalpendu; Pathak, Soham; Yanushefski, Katherine A., Sub-micron planar lightwave devices formed on an SOI optical platform.

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137. Bedell,Stephen W.; Domenicucci,Anthony G.; Fogel,Keith E.; Leobandung,Effendi; Sadana,Devendra K., Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer.

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138. Bedell,Stephen W.; Domenicucci,Anthony G.; Fogel,Keith E.; Leobandung,Effendi; Sadana,Devendra K., Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer.

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139. Zhu, Huilong; Luo, Zhijiong, finFET structure with multiply stressed gate electrode.

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