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Multi-chip module structure having conductive blocks to provide electrical connection between conductors on first and second sides of a conductive base substrate 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/34
출원번호 US-0485400 (2000-02-10)
우선권정보 JP-9-222229 (1997-08-19); JP-9-259589 (1997-09-25); JP-10-069727 (1998-03-19)
국제출원번호 PCT/JP98/03668 (1998-08-19)
국제공개번호 WO99/09595 (1999-02-25)
발명자 / 주소
  • Kenji Sekine JP
  • Hiroji Yamada JP
  • Matsuo Yamasaki JP
  • Osamu Kagaya JP
  • Kiichi Yamashita JP
출원인 / 주소
  • Hitachi, Ltd. JP
대리인 / 주소
    Antonelli, Terry, Stout & Kraus, LLP
인용정보 피인용 횟수 : 229  인용 특허 : 3

초록

A metal base substrate for mounting a plurality of bare semiconductor chip devices thereon has first and second main surfaces. The first main surface has formed thereon at least one projection, and at least two recesses in which the bare semiconductor chip devices are to be mounted. The depth of the

대표청구항

1. A multi-chip module structure comprising:a conductive base substrate having first and second main surfaces, said first main surface having provided thereon at least two recesses for bare semiconductor chips to be mounted thereon; at least a plurality of said bare semiconductor chips mounted on sa

이 특허에 인용된 특허 (3)

  1. Tetaka Masafumi,JPX ; Maki Shinichiro,JPX ; Ohyama Nobuo,JPX ; Orimo Seiichi,JPX ; Sakoda Hideharu,JPX ; Yoneda Yoshiyuki,JPX ; Shigeno Akihiro,JPX ; Yokoyama Ryoichi,JPX ; Fujisaki Fumitoshi,JPX ; F, Method and apparatus for fabricating semiconductor device.
  2. Ettehadieh Ehsan ; Kaul Sunil ; Malladi Dev, Thermal management enhancements for cavity packages.
  3. Chillara Satya ; Mostafazadeh Shahram, Ultra-thin composite package for integrated circuits.

이 특허를 인용한 특허 (229)

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