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Intermediate-grain reconfigurable processing device 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/00
출원번호 US-0892812 (2001-06-27)
발명자 / 주소
  • Andre DeHon
  • Ethan Mirsky
  • Thomas F. Knight, Jr.
출원인 / 주소
  • Massachusetts Institute of Technology
대리인 / 주소
    Hamilton, Brook, Smith & Reynolds, P.C.
인용정보 피인용 횟수 : 128  인용 특허 : 28

초록

A programmable integrated circuit utilizes a large number of intermediate-grain processing elements which are multibit processing units arranged in a configurable mesh. The coarse-grain resources, such as memory and processing, are deployable in a way that takes advantage of the opportunities for op

대표청구항

1. A programmable integrated circuit comprising:logic units which perform operations on data in response to instructions of a defined set of instructions; memories which store and retrieve data in response to received addresses; a configurable interconnect which provides signal transmission between

이 특허에 인용된 특허 (28)

  1. Deering Michael F. (Mountain View CA), Arithmetic logic system using the output of a first alu to control the operation of a second alu.
  2. Morton Steven G. (Oxford CT), Array reconfiguration apparatus and methods particularly adapted for use with very large scale integrated circuits.
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  7. Casselman Steven Mark (Reseda CA), FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in.
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  11. DeHon Andre ; Mirsky Ethan ; Knight ; Jr. Thomas F., Intermediate-grain reconfigurable processing device.
  12. Wade Jon P. ; Cassiday Daniel R. ; Lordi Robert D. ; Steele ; Jr. Guy Lewis ; St. Pierre Margaret A. ; Wong-Chan Monica C. ; Abuhamdeh Zahi S. ; Douglas David C. ; Ganmukhi Mahesh N. ; Hill Jeffrey V, Massively parallel computer including auxiliary vector processor.
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  18. Zak Robert C. (Lexington MA) Leiserson Charles E. (Winchester MA) Kuzmaul Bradley C. (Waltham MA) Yang Shaw-Wen (Waltham MA) Hillis W. Daniel (Cambridge MA) Douglas David C. (Concord MA) Potter David, Parallel computer system including arrangement for transferring messages from a source processor to selected ones of a p.
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  24. Saccardi Raymond J. (Laurel MD), Reconfigurable pipelined processor.
  25. Gorin Allen L. (Fair Lawn NJ) Makofsky Patrick A. (Randolph NJ) Morton Nancy (Dover NJ) Oliver Neal C. (Madison NJ) Shively Richard R. (Convent Station NJ) Stanziola Christopher A. (Hyde Park NY), Reconfigurable signal processor.
  26. Shindo Tatsuya,JPX ; Kawamura Kaoru,JPX ; Umeda Masanobu,JPX ; Shibuya Toshiyuki ; Miwatari Hideki,JPX, SIMD system having logic units arranged in stages of tree structure and operation of stages controlled through respective control registers.
  27. Gephardt Douglas D. ; Stewart Brett B. ; Wisor Rita M. ; Belt Steven L. ; Dutton Drew J., System for dynamically reconfiguring subbusses of data bus according to system needs based on monitoring each of the inf.
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