$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Structure and method for fabricating an electro-optic system having an electrochromic diffraction grating 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-031/0336
출원번호 US-0908898 (2001-07-20)
발명자 / 주소
  • Lawrence E. Lach
  • Robert Lempkowski
  • Tomasz L. Klosowiak
  • Keryn Lian
출원인 / 주소
  • Motorola, Inc.
대리인 / 주소
    Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
인용정보 피인용 횟수 : 173  인용 특허 : 78

초록

A semiconductor structure for implementing optical beam switching includes a monocrystalline silicon substrate and an amorphous oxide material overlying the monocrystalline silicon substrate. A monocrystalline perovskite oxide material overlies the amorphous oxide material and a monocrystalline comp

대표청구항

1. A semiconductor structure comprising:a monocrystalline silicon substrate; an amorphous oxide material overlying the monocrystalline silicon substrate; a monocrystalline perovskite oxide material overlying the amorphous oxide material; a monocrystalline compound semiconductor material overlying th

이 특허에 인용된 특허 (78)

  1. Qureshi Shahid U. H. (Natick MA) Seitz Karl W. (Norfolk MA) Wilson Robert M. (Walpole MA), Adaptive communication rate modem.
  2. Jin Sungho (Millington NJ) McCormack Mark T. (Summit NJ) Ramesh Ramamoorthy (Tinton Falls NJ), Article comprising magnetoresistive material.
  3. Yamakido Kazuo (Hinode JPX) Kobayashi Yoichiro (Ohme JPX) Otsuka Masanori (Kokubunji JPX) Okazaki Takao (Hamura JPX) Ishihara Yukihito (Ohme JPX) Nishikawa Norimitsu (Ohme JPX) Tamba Yuko (Ohme JPX), Converter, offset adjustor, and portable communication terminal unit.
  4. Krivokapic Zoran, Convex device with selectively doped channel.
  5. Reinhart Franz K. (Summit NJ), Electro-optic polarization modulation in multi-electrode waveguides.
  6. Kashihara Keiichiro (Hyogo JPX) Okudaira Tomonori (Hyogo JPX) Itoh Hiromi (Hyogo JPX), Electronic device using zirconate titanate and barium titanate ferroelectrics in insulating layer.
  7. Fraden Jacob ; Brown Joseph P. ; Lackey Robert P. ; Howe Randall R. ; Bultges Heinz,DEX ; Debus Wolfram,DEX ; Bautz Gunther,DEX ; Franke Helmut,DEX, Enhanced protective lens cover for an infrared thermometer.
  8. Summerfelt Scott R., Fabricating high-dielectric constant oxides on semiconductors using a GE buffer layer.
  9. Koo Bon-jae,KRX, Ferroelectric memory devices having well region word lines and methods of operating same.
  10. Thomas E. Raymond (Dayton OH) Cahill Lysle D. (Dayton OH) Marshall William W. (Xenia OH) Talley Luke L. (Centerville OH) Lawson John A. (Dayton OH) Wilcox Brian N. (Kettering OH), Flat bed scanner system and method.
  11. Andrews James A. (Phoenix AZ), Flip chip package and method of making.
  12. Kencke David L. ; Banerjee Sanjay K., Floating gate transistor having buried strained silicon germanium channel layer.
  13. Usui Akira,JPX ; Sakai Akira,JPX ; Sunakawa Haruo,JPX ; Mizuta Masashi,JPX ; Matsumoto Yoshishige,JPX, GaN crystal film, a group III element nitride semiconductor wafer and a manufacturing process therefor.
  14. Shi Song Q. (Phoenix AZ), Green-emitting organometallic complexes for use in light emitting devices.
  15. Manchester Kenneth E. (Princeton MA), Hall sensor with integrated pole pieces.
  16. Terranova Nancy (Wilmington DE) Barnett Allen M. (Newark DE), Hetero-epitaxial growth of non-lattice matched semiconductors.
  17. Shen Jun (Phoenix AZ) Tsui Raymond K. (Phoenix AZ) Tehrani Saied N. (Scottsdale AZ) Goronkin Herb (Tempe AZ), Heterojunction interband tunnel diodes with improved P/V current ratios.
  18. Summerfelt Scott R. (Dallas TX), High-dielectric constant oxides on semiconductors using a Ge buffer layer.
  19. Schetzina Jan Frederick (Cary NC), Integrated heterostructures of Group III-V nitride semiconductor materials including epitaxial ohmic contact, non-nitrid.
  20. Tham J. L. Julian ; Mehrotra Deepak ; Bartlett James L. ; Chang Mau Chung F. ; Marcy ; 5th Henry O. ; Pedrotti Kenneth D. ; Pehlke David R. ; Seabury Charles W. ; Yao Jun J., Integrated passive transceiver section.
  21. Stacy Robert A. (St. Louis County MO) Rice Robert R. (Florissant MO), Low voltage electro-optic modulator.
  22. Farb Joseph E. (Riverside CA), Magnetic field detection.
  23. Partin Dale Lee, Magnetic field sensor having high mobility thin indium antimonide active layer on thin aluminum indium antimonide buffer.
  24. Partin Dale L. (Ray MI) Heremans Joseph P. (Troy MI) Green Louis (Rochester Hills MI), Magnetic field sensor on elemental semiconductor substrate with electric field reduction means.
  25. Yamashita Youji (Shizuoka JPX), Method and apparatus for manufacturing semi-insulation GaAs monocrystal.
  26. Haartsen Jacobus,SEX, Method and arrangement for radio communication.
  27. Cook Robert K. (Poughkeepsie) Knepper Ronald W. (Lagrangeville) Kulkarni Subodh K. (Fishkill) Lange Russell C. (Newburgh) Ronsheim Paul A. (Wappingers Falls) Subbanna Seshadri (Hopewell Junction) Tej, Method for controlling interfacial oxide at a polycrystalline/monocrystalline silicon interface.
  28. Yi Zhiyi ; Droopad Ravindranath ; Overgaard Corey Daniel ; Ramdani Jamal ; Curless Jay A. ; Hallmark Jerald A. ; Ooms William J. ; Wang Jun, Method for fabricating a semiconductor structure having a crystalline alkaline earth metal oxide interface with silicon.
  29. Yu Zhiyi ; Droopad Ravindranath ; Overgaard Corey Daniel ; Ramdani Jamal ; Curless Jay A. ; Hallmark Jerald A. ; Ooms William J. ; Wang Jun, Method for fabricating a semiconductor structure having a crystalline alkaline earth metal oxide interface with silicon.
  30. Yu Zhiyi ; Wang Jun ; Droopad Ravindranath ; Ramdani Jamal, Method for fabricating a semiconductor structure having a stable crystalline interface with silicon.
  31. Lee Ming-Tsan,TWX ; Liu Chuan H.,TWX ; Fu Kuan-Yu,TWX, Method for fabricating an oxide layer on silicon with carbon ions introduced at the silicon/oxide interface in order to reduce hot carrier effects.
  32. McGinn Joseph T. (Flemington NJ) Jastrzebski Lubomir L. (Plainsboro NJ) Corboy ; Jr. John F. (Ringoes NJ), Method for growing a low defect monocrystalline layer on a mask.
  33. Suh Jeong-Dae,KRX ; Sung Gun-Yong,KRX, Method for making a superconducting field-effect device with grain boundary channel.
  34. Kizuki Hirotaka,JPX, Method of fabricating a semiconductor device and method of cleaning a crystalline semiconductor surface.
  35. Droopad Ravi ; Abrokwah Jonathan K. ; Passlack Matthias ; Yu Zhiyi Jimmy, Method of forming a silicon nitride layer.
  36. Kiyoku Hiroyuki,JPX ; Nakamura Shuji,JPX ; Kozaki Tokuya,JPX ; Iwasa Naruhito,JPX ; Chocho Kazuyuki,JPX, Method of growing nitride semiconductors, nitride semiconductor substrate and nitride semiconductor device.
  37. Pitt Gillies D. (Saffron Walden GB2) Greene Peter D. (Harlow GB2) Thrush Edward J. (Stansted Mountfitchet GB2) Whysall David H. (Harlow GB2), Method of making a Hall effect device.
  38. Barber Ivor G., Method of packaging integrated circuits.
  39. Takeda Toshikazu (Nagaokakyo JPX) Ogiso Yoshifumi (Nagaokakyo JPX) Nakagawa Takuji (Nagaokakyo JPX) Senda Atsuo (Nagaokakyo JPX), Method of preparing InSb thin film.
  40. Sone Shuji,JPX, Method of producing a thin-film capacitor.
  41. Linthicum Kevin J. ; Gehrke Thomas ; Davis Robert F. ; Thomson Darren B. ; Tracy Kieran M., Methods of fabricating gallium nitride microelectronic layers on silicon layers and gallium nitride microelectronic structures formed thereby.
  42. Tsuzuki Koji,JPX ; Murakami Tsutomu,JPX ; Yamada Satoru,JPX ; Takeyama Yoshifumi,JPX ; Shimizu Koichi,JPX, Moldless semiconductor device and photovoltaic device module making use of the same.
  43. Bayraktaroglu Burhan (Plano TX), Monolithic microwave transmitter/receiver.
  44. Hovel Harold J. (Katonah NY), Multiple bandgap solar cell on transparent substrate.
  45. Imai Hideaki (Fuji JPX) Miyata Kunio (Kyoto JPX) Hirai Tadahiko (Koganei JPX), Nitride based semiconductor device and manufacture thereof.
  46. Nakamura Shuji,JPX ; Nagahama Shinichi,JPX ; Iwasa Naruhito,JPX ; Kiyoku Hiroyuki,JPX, Nitride semiconductor light-emitting device.
  47. Nunoue Shinya,JPX ; Yamamoto Masahiro,JPX, Nitride-compound semiconductor device.
  48. Mehrgardt Soenke (March-Meuershausen DEX) Blossfeld Lothar (Freiburg-Hochdorf DEX), Offset-compensated hall sensor having plural hall detectors having different geometrical orientations and having switcha.
  49. Nashimoto Keiichi,JPX ; Watanabe Masao,JPX ; Moriyama Hiroaki,JPX ; Nakamura Shigetoshi,JPX ; Osakabe Eisuke,JPX ; Morikawa Takashi,JPX, Opical waveguide device.
  50. Van De Voorde Ingrid Zulma Benoit,BEX ; Van Der Plas Gert,BEX, Optical amplifier combiner arrangement and method for upstream transmission realized thereby.
  51. Giles Clinton R. (Middletown NJ) Li Tingye (Rumson NJ) Wood Thomas H. (Highlands NJ), Optical communication by injection-locking to a signal which modulates an optical carrier.
  52. Ho Steven H. (Urbana IL) Conforti Evandro (Campinas BRX) Kang Sung M. (Champaign IL), Optical communications and interconnection networks having opto-electronic switches and direct optical routers.
  53. Yano Yutaka,JPX, Optical regenerative repeater.
  54. Hunsperger Robert G. (Newark DE) Maltenfort Andrew J. (New Castle DE), Optical wavelength division multiplexing/demultiplexing system.
  55. Shi Song Q. (4521 E. Gold Poppy Way Phoenix AZ 85283), Organometallic complexes with built-in fluorescent dyes for use in light emitting devices.
  56. Shi Song Q. (Phoenix AZ) So Franky (Tempe AZ), Organometallic fluorescent complex polymers for light emitting applications.
  57. Nashimoto Keiichi (Minami Ashigara JPX), Oriented conductive film and process for preparing the same.
  58. Summerfelt Scott R. (Dallas TX), Pb/Bi-containing high-dielectric constant oxides using a non-Pb/Bi-containing perovskite as a buffer layer.
  59. Nause Jeffrey E. ; Hill D. Norman ; Pope Stephen G., Pressurized skull crucible for crystal growth using the Czochralski technique.
  60. Rostoker Michael D. (San Jose CA) Pasch Nicholas F. (Pacifica CA), Process for solder ball interconnecting a semiconductor device to a substrate using a noble metal foil embedded interpos.
  61. Ariyoshi Hisashi (Tokyo JPX) Kasanami Toru (Kyoto JPX) Fukuda Susumu (Osaka JPX), Producing a compound semiconductor device on an oxygen implanted silicon substrate.
  62. Fafard Simon,CAX ; Liu Hui Chun,CAX, Quantum dot infrared photodetectors (QDIP).
  63. Heremans Joseph P. (Troy MI) Partin Dale L. (Romeo MI) Thrush Christopher M. (Shelby Township MI), Rare earth slab doping of group III-V compounds.
  64. Toh Chai Keong,SGX, Routing method for Ad-Hoc mobile networks.
  65. Gilboa Yitzhak Eric ; Brosilow Benjamin,ILX ; Levy Sagy ; Spielberg Hedvi ; Bransky Itai,ILX, Selective hemispherical grain silicon deposition.
  66. Soref Richard A. (Newton Centre MA) Taylor Henry F. (College Station TX), Semiconductive guided-wave programmable optical delay lines using electrooptic fabry-perot elements.
  67. Nishimura Takashi (Itami JPX), Semiconductor device.
  68. Yanagase Masashi (Tsukuba JPX) Watanabe Hideaki (Tsukuba JPX) Imamaka Koichi (Tsukuba JPX), Semiconductor luminous element with light reflection and focusing configuration.
  69. Shibasaki Ichiro (Fuji JPX) Kuze Naohiro (Fuji JPX) Iwabuchi Tatsuro (Fuji JPX) Nagase Kazuhiro (Fuji JPX), Semiconductor sensors and method for fabricating the same.
  70. Wang Jun ; Ooms William Jay ; Hallmark Jerald Allen, Semiconductor structure having a crystalline alkaline earth metal oxide interface with silicon.
  71. Shi Song Q. (Phoenix AZ), Soluble precursor to poly (cyanoterephthalydene) and method of preparation.
  72. McKee Rodney Allen ; Walker Frederick Joseph, Strain-based control of crystal anisotropy for perovskite oxides on semiconductor-based material.
  73. Tetsuzo Yoshimura ; Yashuhito Takahashi ; Masaaki Inao ; Michael G. Lee ; William Chou ; Solomon I. Beilin ; Wen-chou Vincent Wang ; James J. Roman ; Thomas J. Massingill, Systems based on opto-electronic substrates with electrical and optical interconnections and methods for making.
  74. Tseng T. J.,TWX ; Cheng David C. H.,TWX, Thermal vias-provided cavity-down IC package structure.
  75. Sone Shuji,JPX ; Kato Yoshitake,JPX, Thin film capacitor including perovskite-type oxide layers having columnar structure and granular structure.
  76. Hoole Elliott D., Transmit/receive compensation.
  77. Lehovec Kurt (Los Angeles CA), Tunnel diode load for ultra-fast low power switching circuits.
  78. Koch Thomas L. (Holmdel NJ), Wavelength division multiplexed optical communication transmitters.

이 특허를 인용한 특허 (173)

  1. Chen, Xiangdong; Dyer, Thomas W.; Settlemyer, Kenneth; Yang, Haining S., CMOS devices with stressed channel regions, and methods for fabricating the same.
  2. Zhu, Huilong; Yang, Baewon, CMOS structures and methods for improving yield.
  3. Zhu, Huilong; Yang, Daewon, CMOS structures and methods for improving yield.
  4. Zhu, Huilong; Yang, Daewon, CMOS structures and methods using self-aligned dual stressed layers.
  5. Ryou,Jae Hyun; Park,Gyoungwon, Dielectric VCSEL gain guide.
  6. Zhu,Huilong; Doris,Bruce B.; Chen,Huajie, Dislocation free stressed channels in bulk silicon and SOI CMOS devices by gate stress engineering.
  7. Fang, Sunfei; Kim, Jun Jung; Luo, Zhijiong; Ng, Hung Y.; Rovedo, Nivo; Teh, Young Way, Dual stress memory technique method and related structure.
  8. Chidambarrao,Dureseti; Dokumaci,Omer H.; Doris,Bruce B.; Gluschenkov,Oleg; Zhu,Huilong, Dual stressed SOI substrates.
  9. Chidambarrao,Dureseti; Doris,Bruce B.; Gluschenkov,Oleg; Dokumaci,Omer H.; Zhu,Huilong, Dual stressed SOI substrates.
  10. Li, Bernard Q., Edge bead control method and apparatus.
  11. Giron, Jean-Christophe; Gy, René; Bertin-Mourot, Thomas, Electrochromic device.
  12. Burdis, Mark Samuel; Greer, Bryan D.; Weir, Douglas Glenn John, Electrochromic devices having improved ion conducting layers.
  13. Burdis, Mark Samuel; Greer, Bryan D.; Weir, Douglas Glenn John, Electrochromic devices having improved ion conducting layers.
  14. Burdis, Mark Samuel; Greer, Bryan D.; Weir, Douglas Glenn John, Electrochromic devices having improved ion conducting layers.
  15. Li, Changfeng; Dong, Xue; Wang, Haisheng; Chen, Xiaochuan; Zhao, Wenqing; Liu, Yingming; Yang, Shengji; Yang, Ming; Li, Mubing, Electrochromic grating, display panel and display device.
  16. Biard,James R.; Johnson,Ralph H.; Johnson,Klein L., Electron affinity engineered VCSELs.
  17. Katoda, Takashi, Electronic devices formed on substrates and their fabrication methods.
  18. Towle,Steven, Electrooptic assembly.
  19. Chidambarrao,Dureseti, Enhanced PFET using shear stress.
  20. Ryou,Jae Hyun; Wang,Tzu Yu; Kim,Jin K.; Park,Gyoungwon; Kwon,Hoki, Enhanced lateral oxidation.
  21. Passlack, Matthias; Hartin, Olin L.; Ray, Marcus; Medendorp, Nicholas, Enhancement mode metal-oxide-semiconductor field effect transistor.
  22. Vieira,Amarildo J. C.; Barenburg,Barbara F.; Brophy,Timothy J., Fabrication of a wavelength locker within a semiconductor structure.
  23. Liang, Yong; Droopad, Ravindranath; Li, Hao; Yu, Zhiyi, Ferromagnetic semiconductor structure and method for forming the same.
  24. Zhu, Huilong; Luo, Zhijiong, FinFET structure with multiply stressed gate electrode.
  25. Chidambarrao, Dureseti, Gate electrode stress control for finFET performance enhancement.
  26. El Zein,Nada; Ramdani,Jamal; Eisenbeiser,Kurt; Droopad,Ravindranath, Heterojunction tunneling diodes and process for fabricating same.
  27. Doris, Bruce B.; Gluschenkov, Oleg G.; Zhu, Huilong, High mobility CMOS circuits.
  28. Doris,Bruce B.; Gluschenkov,Oleg G.; Zhu,Huilong, High mobility CMOS circuits.
  29. Doris,Bruce B.; Gluschenkov,Oleg G.; Zhu,Huilong, High mobility CMOS circuits.
  30. Doris,Bruce B.; Chidambarrao,Dureseti; Ku,Suk Hoon, High performance CMOS device structures and method of manufacture.
  31. Doris,Bruce B.; Chidambarrao,Dureseti; Ku,Suk Hoon, High performance CMOS device structures and method of manufacture.
  32. Doris, Bruce B; Gluschenkov, Oleg G, High performance strained CMOS devices.
  33. Doris,Bruce B.; Gluschenkov,Oleg G., High performance strained CMOS devices.
  34. Chidambarrao, Dureseti; Donaton, Ricardo A.; Henson, William K.; Rim, Kern, High performance stress-enhance MOSFET and method of manufacture.
  35. Chidambarrao, Dureseti; Donaton, Ricardo A.; Henson, William K.; Rim, Kern, High performance stress-enhance MOSFET and method of manufacture.
  36. Chidambarrao, Dureseti; Donaton, Ricardo A.; Henson, William K.; Rim, Kern, High performance stress-enhance MOSFET and method of manufacture.
  37. Chen, Huajie; Chidambarrao, Dureseti; Dokumaci, Omer H., High performance stress-enhanced MOSFETS using Si:C and SiGe epitaxial source/drain and method of manufacture.
  38. Chen, Huajie; Chidambarrao, Dureseti; Dokumaci, Omer H., High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture.
  39. Chen, Huajie; Chidambarrao, Dureseti; Dokumaci, Omer H., High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture.
  40. Chen, Huajie; Chidambarrao, Dureseti; Dokumaci, Omer H., High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture.
  41. Chen,Huajie; Chidambarrao,Dureseti; Dokumaci,Omer H, High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture.
  42. Cox, James A.; Chen, Bo Su, High speed optical system.
  43. Havens, William H.; Cairns, James A., High-efficiency illumination in data collection devices.
  44. Doris, Bruce B.; Guarini, Kathryn W.; Ieong, Meikei; Narasimha, Shreesh; Rim, Kern; Sleight, Jeffrey W.; Yang, Min, High-performance CMOS SOI devices on hybrid crystal-oriented substrates.
  45. Doris,Bruce B.; Guarini,Kathryn W.; Ieong,Meikei; Narasimha,Shreesh; Rim,Kern; Sleight,Jeffrey W.; Yang,Min, High-performance CMOS devices on hybrid crystal oriented substrates.
  46. Zhu,Huilong; Oldiges,Philip J.; Doris,Bruce B.; Wang,Xinlin; Gluschenkov,Oleg; Chen,Huajie; Zhang,Ying, Hybrid SOI-bulk semiconductor transistors.
  47. Zhu, Huilong; Oldiges, Philip J.; Doris, Bruce B.; Wang, Xinlin; Gluschenkov, Oleg; Chen, Huajie; Zhang, Ying, Hybrid SOI/bulk semiconductor transistors.
  48. Wang,Tzu Yu; Kwon,Hoki; Ryou,Jae Hyun; Park,Gyoungwon; Kim,Jin K., InP based long wavelength VCSEL.
  49. Biard,James R.; Johnson,Klein L.; Johnson,Ralph H.; Park,Gyoungwon; Wang,Tzu Yu, Long wavelength VCSEL device processing.
  50. Johnson, Ralph H.; Wang, Tzu-Yu, Long wavelength VCSEL with tunnel junction, and implant.
  51. Chidambarrao, Dureseti; Dokumaci, Omer H., MOSFET performance improvement using deformation in SOI structure.
  52. Chidambarrao, Dureseti; Dokumaci, Omer H., MOSFET performance improvement using deformation in SOI structure.
  53. Yang, Haining S.; Zhu, Huilong, Method and apparatus for increase strain effect in a transistor channel.
  54. Yang,Haining S.; Zhu,Huilong, Method and apparatus for increase strain effect in a transistor channel.
  55. Yang,Haining S.; Zhu,Huilong, Method and apparatus to increase strain effect in a transistor channel.
  56. Ooms,William J.; Hallmark,Jerald A., Method and apparatus utilizing monocrystalline insulator.
  57. Yang,Haining S.; Zhu,Huilong, Method and structure for controlling stress in a transistor channel.
  58. Steegen, An L.; Yang, Haining S.; Zhang, Ying, Method and structure for forming strained SI for CMOS devices.
  59. Steegen,An L; Yang,Haining S.; Zhang,Ying, Method and structure for forming strained SI for CMOS devices.
  60. Steegen, An L.; Yang, Haining S.; Zhang, Ying, Method and structure for forming strained Si for CMOS devices.
  61. Steegen,An L.; Yang,Haining S.; Zhang,Ying, Method and structure for forming strained Si for CMOS devices.
  62. Yang, Haining S.; Lim, Eng Hua, Method and structure for forming strained devices.
  63. Chidambarrao, Dureseti; Dokumaci, Omer H., Method and structure for improved MOSFETs using poly/silicide gate height control.
  64. Chidambarrao,Dureseti; Dokumaci,Omer H., Method and structure for improved MOSFETs using poly/silicide gate height control.
  65. Chidambarrao, Dureseti; Greene, Brian J., Method and structure for improving device performance variation in dual stress liner technology.
  66. Chidambarrao,Dureseti; Greene,Brian J., Method and structure for improving device performance variation in dual stress liner technology.
  67. Liang,Yong; Droopad,Ravindranath; Hu,Xiaoming; Wang,Jun; Wei,Yi; Yu,Zhiyi, Method for fabricating semiconductor structures on vicinal substrates using a low temperature, low pressure, alkaline earth metal-rich process.
  68. Johansson, Ted, Method for fabrication of a capacitor, and a monolithically integrated circuit comprising such a capacitor.
  69. Chen, Wanshi; Zhang, Wang, Method for forming current diffusion layer in light emitting diode device and method for fabricating the same.
  70. Li, Hao; Droopad, Ravindranath; Marshall, Daniel S.; Wei, Yi; Hu, Xiao M.; Liang, Yong, Method for growing a monocrystalline oxide layer and for fabricating a semiconductor device on a monocrystalline substrate.
  71. Chidambarrao,Dureseti; Dokumaci,Omer H., Method for reduced N+ diffusion in strained Si on SiGe substrate.
  72. Chidambarrao,Dureseti; Dokumaci,Omer H., Method for reduced N+ diffusion in strained Si on SiGe substrate.
  73. Chidambarrao,Dureseti; Dokumaci,Omer H., Method for reduced N+ diffusion in strained Si on SiGe substrate.
  74. Belyansky,Michael P.; Doris,Bruce B.; Gluschenkov,Oleg, Method of fabricating mobility enhanced CMOS devices.
  75. Chen, Huajie; Chidambarrao, Dureseti; Holt, Judson R.; Ouyang, Qiqing C.; Panda, Siddhartha, Method of forming a cross-section hourglass shaped channel region for charge carrier mobility modification.
  76. Chen,Xiaomeng; Jeng,Shwu Jen; Kim,Byeong Y.; Nayfeh,Hasan M., Method of making a semiconductor structure.
  77. Cheng,Kangguo; Chidambarrao,Dureseti, Method of manufacturing a strained silicon on a SiGe on SOI substrate.
  78. Chidambarrao,Dureseti; Dokumaci,Omer H., Method of manufacturing strained dislocation-free channels for CMOS.
  79. Yang, Haining S.; Panda, Siddhartha, Method to increase strain enhancement with spacerless FET and dual liner process.
  80. Guarin, Fernando; Hostetter, Jr., J. Edwin; Rauch, III, Stewart E.; Wang, Ping-Chuan; Yang, Zhijian J., Methodology for recovery of hot carrier induced degradation in bipolar devices.
  81. Cox,James A.; Chen,Bo Su, Methods for signal transmission in optical fiber.
  82. Belyansky, Michael P.; Doris, Bruce B.; Gluschenkov, Oleg G., Mobility enhanced CMOS devices.
  83. Adam, Thomas N.; Chidambarrao, Dureseti, Mobility enhancement in SiGe heterojunction bipolar transistors.
  84. Chidambarrao,Dureseti; Dokumaci,Omer H.; Gluschenkov,Oleg G., NFETs using gate induced stress modulation.
  85. Blasingame,Raymond W.; Lee,James C.; Li,Bernard Q., Optical coupling system.
  86. Wang, Dongdong; Shao, Zhenhua; Huang, Xu; Ito, Masataka; Keller, Christopher L., Optical interconnect device and method for manufacturing the same.
  87. Wang, Dongdong; Shao, Zhenhua; Huang, Xu; Ito, Masataka; Keller, Christopher L., Optical interconnect device and method for manufacturing the same.
  88. Wang, Dongdong; Shao, Zhenhua; Huang, Xu; Ito, Masataka; Keller, Christopher Lee, Optical interconnect device and method for manufacturing the same.
  89. Wang, Dongdong; Shao, Zhenhua; Huang, Xu; Ito, Masataka; Keller, Christopher Lee, Optical interconnect device and method for manufacturing the same.
  90. Chen,Bo Su, Optical system with reduced back reflection.
  91. Talin,Albert Alec; Voight,Steven A., Optical waveguide structure and method for fabricating the same.
  92. Cheng, Kangguo; Divakaruni, Ramachandra, Patterned strained semiconductor substrate and device.
  93. Cheng, Kangguo; Divakaruni, Ramachandra, Patterned strained semiconductor substrate and device.
  94. Cheng, Kangguo; Divakaruni, Ramachandra, Patterned strained semiconductor substrate and device.
  95. Cheng,Kangguo; Divakaruni,Ramachandra, Patterned strained semiconductor substrate and device.
  96. Katoda, Takashi, Photonic devices formed of high-purity molybdenum oxide.
  97. Katoda, Takashi, Photonic devices formed on substrates and their fabrication methods.
  98. Blasingame,Raymond W.; Chen,Bo Su; Lee,James C.; Orenstein,James D.; Guenter,James K., Pluggable optical optic system having a lens fiber stop.
  99. Yao, Liang-Gi; Wang, Ming-Fang; Chen, Shih-Chang; Liang, Mong-Song, Process to make high-K transistor dielectrics.
  100. Yao, Liang-Gi; Wang, Ming-Fang; Chen, Shih-Chang; Liang, Mong-Song, Process to make high-K transistor dielectrics.
  101. Yao,Liang Gi; Wang,Ming Fang; Chen,Shih Chang; Liang,Mon Song, Process to make high-k transistor dielectrics.
  102. Zhu,Huilong; Doris,Bruce B.; Mocuta,Dan M., Protecting silicon germanium sidewall with silicon for strained silicon/silicon mosfets.
  103. Chidambarrao, Dureseti; Mocuta, Anda C.; Mocuta, Dan M.; Radens, Carl, Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain.
  104. Chidambarrao, Dureseti; Mocuta, Anda C.; Mocuta, Dan M.; Radens, Carl, Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain.
  105. Beintner,Jochen; Bronner,Gary B.; Divakaruni,Ramachandra; Kim,Byeong Y., Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI structure with elevated source/drain.
  106. Chidambarrao,Dureseti, Rotational shear stress for charge carrier mobility modification.
  107. Chidambarrao,Dureseti, Rotational shear stress for charge carrier mobility modification.
  108. Deshpande,Sadanand V.; Doris,Bruce B.; Rausch,Werner A.; Slinkman,James A., STI stress modification by nitrogen plasma treatment for improving performance in small width devices.
  109. Eisenbeiser,Kurt; Wang,Jun; Droopad,Ravindranath, Semiconductor device and method.
  110. Chen, Xiangdong; Yang, Haining S., Semiconductor device structure having enhanced performance FET device.
  111. Arnold, John C.; Chidambarrao, Dureseti; Li, Ying; Malik, Rajeev; Narasimha, Shreesh; Panda, Siddhartha; Tessier, Brian L.; Wise, Richard, Semiconductor device structure having low and high performance devices of same conductive type on same substrate.
  112. Yu,Zhiyi; Droopad,Ravindranath, Semiconductor structure exhibiting reduced leakage current and method of fabricating same.
  113. Chen, Xiaomeng; Jeng, Shwu-Jen; Kim, Byeong Y.; Nayfeh, Hasan M., Semiconductor structure having undercut-gate-oxide gate stack enclosed by protective barrier material.
  114. Ramdani,Jamal; Droopad,Ravindranath; Hilt,Lyndee L.; Eisenbeiser,Kurt Williamson, Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same.
  115. Zhu, Huilong; Greene, Brian J.; Chidambarrao, Dureseti; Freeman, Gregory G., Semiconductor-on-insulator structures including a trench containing an insulator stressor plug and method of fabricating same.
  116. Chidambarrao, Dureseti; Dokumaci, Omer H.; Rengarajan, Rajesh; Steegen, An L., Silicide proximity structures for CMOS device performance improvements.
  117. Chidambarrao, Dureseti; Dokumaci, Omer H.; Gluschenkov, Oleg, Silicon device on SI:C-OI and SGOI and method of manufacture.
  118. Chidambarrao, Duresti; Dokumaci, Omer H.; Gluschenkov, Oleg G., Silicon device on Si: C-oi and Sgoi and method of manufacture.
  119. Chidambarrao, Dureseti; Dokumaci, Omer H.; Gluschenkov, Oleg G., Silicon device on Si:C SOI and SiGe and method of manufacture.
  120. Chidambarrao, Dureseti; Dokumaci, Omer H.; Gluschenkov, Oleg G., Silicon device on Si:C-OI and SGOI and method of manufacture.
  121. Chidambarrao,Dureseti; Dokumaci,Omer H.; Gluschenkov,Oleg G., Silicon device on Si:C-OI and SGOI and method of manufacture.
  122. Tatum, James A.; Guenter, James K; Johnson, Ralph H., Single mode VCSEL.
  123. Ajmera, Atul C.; Baiocco, Christopher V.; Chen, Xiangdong; Gao, Wenzhi; Teh, Young Way, Spacer and process to enhance the strain in the channel with stress liner.
  124. Lu, Wen; Mattes, Benjamin R.; Fadeev, Andrei G.; Qi, Baohua, Stable conjugated polymer electrochromic devices incorporating ionic liquids.
  125. de Souza, Joel P.; Hamaguchi, Masafumi; Ozcan, Ahmet S.; Sadana, Devendra K.; Saenger, Katherine L.; Wall, Donald R., Strain preserving ion implantation methods.
  126. Chan, Kevin K.; Chu, Jack O.; Rim, Kern; Shi, Leathen, Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI).
  127. Chan,Kevin K.; Chan,Jack Q; Rim,Kern; Shi,Leathen, Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI).
  128. Chan,Kevin K.; Chu,Jack O.; Rim,Kern; Shi,Leathen, Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI).
  129. Chan,Kevin K.; Chu,Jack O.; Rim,Kern; Shi,Leathen, Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI).
  130. Chidambarrao, Dureseti; Dokumaci, Omer H.; Gluschenkov, Oleg G.; Zhu, Huilong, Strained Si on multiple materials for bulk or SOI substrates.
  131. Chidambarrao,Dureseti; Dokumaci,Omer H.; Gluschenkov,Oleg G.; Zhu,Huilong, Strained Si on multiple materials for bulk or SOI substrates.
  132. Chidambarrao,Dureseti; Dokumaci,Omer H., Strained dislocation-free channels for CMOS and method of manufacture.
  133. Doris,Bruce B.; Chidambarrao,Dureseti; Ieong,MeiKei; Mandelman,Jack A., Strained finFET CMOS device structures.
  134. Chidambarrao,Dureseti; Dokumaci,Omer H.; Gluschenkov,Oleg G., Strained finFETs and method of manufacture.
  135. Cheng,Kangguo; Chidambarrao,Dureseti, Strained silicon on a SiGe on SOI substrate.
  136. Chidambarrao, Dureseti; Dokumaci, Omer H., Strained silicon on relaxed sige film with uniform misfit dislocation density.
  137. Bryant, Andres; Ouyang, Qiqing; Rim, Kern, Strained-silicon CMOS device and method.
  138. Bryant,Andres; Ouyang,Qiqing; Rim,Kern, Strained-silicon CMOS device and method.
  139. Chidambarrao, Dureseti; Henson, William K.; Rim, Kern; Wille, William C., Stress engineering using dual pad nitride with selective SOI device architecture.
  140. Chidambarrao,Dureseti; Henson,William K.; Rim,Kern; Wille,William C., Stress engineering using dual pad nitride with selective SOI device architecture.
  141. Zhu, Huilong; Wang, Jing, Stress-generating shallow trench isolation structure having dual composition.
  142. Zhu, Huilong; Wang, Jing, Stress-generating shallow trench isolation structure having dual composition.
  143. Zhu, Huilong; Wang, Jing, Stress-generating shallow trench isolation structure having dual composition.
  144. Zhu, Huilong; Greene, Brian J.; Chidambarrao, Dureseti; Freeman, Gregory G., Stress-generating structure for semiconductor-on-insulator devices.
  145. Zhu, Huilong; Greene, Brian J.; Chidambarrao, Dureseti; Freeman, Gregory G., Stress-generating structure for semiconductor-on-insulator devices.
  146. Doris,Bruce B.; Belyansky,Michael P.; Boyd,Diane C.; Chidambarrao,Dureseti; Gluschenkov,Oleg, Stressed semiconductor device structures having granular semiconductor material.
  147. Doris,Bruce B; Belyansky,Michael P; Boyd,Diane C; Chidambarrao,Dureseti; Gluschenkov,Oleg, Stressed semiconductor device structures having granular semiconductor material.
  148. Ramdani,Jamal; Hilt,Lyndee L., Structure and method for fabricating GaN devices utilizing the formation of a compliant substrate.
  149. Emrick, Rudy M.; Bosco, Bruce Allen; Holmes, John E.; Franson, Steven James; Rockwell, Stephen Kent, Structure and method for fabricating configurable transistor devices utilizing the formation of a compliant substrate for materials used to form the same.
  150. Holm, Paige M.; Barenburg, Barbara Foley; Yamamoto, Joyce K.; Richard, Fred V., Structure and method for fabricating semiconductor microresonator devices.
  151. Lempkowski,Robert; Chason,Marc, Structure and method for fabricating semiconductor structures and devices for detecting an object.
  152. Tungare,Aroon; Klosowiak,Tomasz L., Structure and method for fabricating semiconductor structures and devices utilizing piezoelectric materials.
  153. Zhu,Huilong; Doris,Bruce B.; Oldiges,Philip J.; Ieong,Meikei; Yang,Min; Chen,Huajie, Structure and method for manufacturing planar strained Si/SiGe substrate with multiple orientations and different stress levels.
  154. Zhu,Huilong; Doris,Bruce B., Structure and method for manufacturing strained FINFET.
  155. Zhu,Huilong; Doris,Bruce B., Structure and method for manufacturing strained FINFET.
  156. Chan,Victor W. C.; Lee,Yong M.; Yang,Haining, Structure and method of applying stresses to PFET and NFET transistor channels for improved performance.
  157. Cabral, Jr.,Cyril; Doris,Bruce B.; Kanarsky,Thomas S.; Liu,Xiao H.; Zhu,Huilong, Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification.
  158. Yang,Haining S.; Zhu,Huilong, Structure and method to induce strain in a semiconductor device channel with stressed film under the gate.
  159. Chen,Xiangdong; Yang,Haining S., Structure and method to optimize strain in CMOSFETs.
  160. Yang, Haining; Li, Wai-Kin, Structure and method to use low k stress liner to reduce parasitic capacitance.
  161. Cheng,Kangguo; Chidambarrao,Dureseti; Divakaruni,Rama; Gluschenkov,Oleg G., Structure of vertical strained silicon devices.
  162. Zhu, Huilong; Bedell, Steven W.; Doris, Bruce B.; Zhang, Ying, Structures and methods for making strained MOSFETs.
  163. Zhu,Hiulong; Bedell,Steven W.; Doris,Bruce B.; Zhang,Ying, Structures and methods for making strained MOSFETs.
  164. Zhu,Huilong; Doris,Bruce B.; Chen,Huajie, Structures and methods for manufacturing of dislocation free stressed channels in bulk silicon and SOI CMOS devices by gate stress engineering with SiGe and/or Si:C.
  165. Zhu, Huilong; Doris, Bruce B.; Chen, Huajie, Structures and methods for manufacturing of dislocation free stressed channels in bulk silicon and SOI MOS devices by gate stress engineering with SiGe and/or Si:C.
  166. Zhu,Huilong, Structures and methods for manufacturing p-type MOSFET with graded embedded silicon-germanium source-drain and/or extension.
  167. Bedell,Stephen W.; Domenicucci,Anthony G.; Fogel,Keith E.; Leobandung,Effendi; Sadana,Devendra K., Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer.
  168. Bedell,Stephen W.; Domenicucci,Anthony G.; Fogel,Keith E.; Leobandung,Effendi; Sadana,Devendra K., Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer.
  169. Ryou,Jae Hyun; Ringle,Michael D.; Liu,Yue, VCSEL having thermal management.
  170. Johnson, Ralph H.; Morales, Gilberto, Versatile method and system for single mode VCSELs.
  171. Johnson,Ralph H.; Morales,Gilberto, Versatile method and system for single mode VCSELs.
  172. Johnson,Ralph H.; Morales,Gilberto, Versatile method and system for single mode VCSELs.
  173. Zhu, Huilong; Luo, Zhijiong, finFET structure with multiply stressed gate electrode.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로