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Process to increase reliability CuBEOL structures 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0677585 (2000-10-03)
발명자 / 주소
  • Chen, Xiaomeng
  • Krishnan, Mahadevaiyer
  • Rubino, Judith M.
  • Sambucetti, Carlos J.
  • Seo, Soon-Cheon
  • Tornello, James A.
출원인 / 주소
  • International Business Machines Corp.
대리인 / 주소
    Connolly Bove Lodge & Hutz, LLP
인용정보 피인용 횟수 : 25  인용 특허 : 10

초록

The invention provides a process to increase the reliability of BEOL interconnects. The process comprises forming an array of conductors on a dielectric layer on a wafer substrate, polishing the upper surface so that the surfaces of the conductors are substantially co-planar with the upper surface o

대표청구항

1. A process to increase the reliability of Cu-BEOL interconnects comprising: forming an array of conductors on a dielectric layer on a wafer substrate; polishing the upper surface of said conductors so that said upper surface of said conductors is substantially co-planar with the upper surface

이 특허에 인용된 특허 (10)

  1. Avanzino Steven C. ; Erb Darrell M. ; Schonauer Diana M. ; Yang Kai, Chemically removable Cu CMP slurry abrasive.
  2. Avanzino Steven C. ; Erb Darrell M. ; Schonauer Diana M. ; Yang Kai, Chemically removable Cu CMP slurry abrasive.
  3. Li Xu ; Zhao Yuexing ; Hymes Diane J. ; de Larios John M., Cleaning solution and method for cleaning semiconductor substrates after polishing of cooper film.
  4. Schonauer Diana M. ; Avanzino Steven C. ; Yang Kai, Copper dendrite prevention by chemical removal of dielectric.
  5. Omura Masayoshi,JPX, Damascene wiring with flat surface.
  6. Komiya Takayuki,JPX ; Kawano Yumiko,JPX, Method for forming multilevel interconnection of semiconductor device.
  7. Watanabe Yoshio,JPX ; Kawashima Kenichi,JPX, Method of fabricating a semiconductor device using a CMP process.
  8. Ngo Minh Van ; Wang Fei, Method of forming copper interconnects with reduced in-line diffusion.
  9. Andreas Michael T., Methods and solutions for cleaning polished aluminum-containing layers, methods for making metallization structures, and the structures resulting from these methods.
  10. Kondo Seiichi,JPX ; Homma Yoshio,JPX ; Sakuma Noriyuki,JPX ; Takeda Kenichi,JPX ; Hinode Kenji,JPX, Polishing method.

이 특허를 인용한 특허 (25)

  1. Weiner, Kurt H.; Chiang, Tony P.; Francis, Aaron; Schmidt, John, Advanced mixing system for integrated tool having site-isolated reactors.
  2. Farkas, Janos; Michaelson, Lynne M; Kordic, Srdjan, Capping layer formation onto a dual damescene interconnect.
  3. Weidman, Timothy W.; Wijekoon, Kapila P.; Zhu, Zhize; Gelatos, Avgerinos V. (Jerry); Khandelwal, Amit; Shanmugasundram, Arulkumar; Yang, Michael X.; Mei, Fang; Moghadam, Farhad K., Contact metallization scheme using a barrier layer over a silicide layer.
  4. Stewart, Michael P.; Weidman, Timothy W.; Shanmugasundram, Arulkumar; Eaglesham, David J., Electroless deposition process on a silicon contact.
  5. Stewart, Michael P.; Weidman, Timothy W.; Shanmugasundram, Arulkumar; Eaglesham, David J., Electroless deposition process on a silicon contact.
  6. Lazovsky, David E.; Malhotra, Sandra G.; Boussie, Thomas R., Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region.
  7. Lazovsky, David E.; Malhotra, Sandra G.; Boussie, Thomas R., Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region.
  8. Lazovsky,David E.; Malhotra,Sandra G.; Boussie,Thomas R., Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region.
  9. Daubenspeck, Timothy H.; Landers, William F.; Zupanski-Nielsen, Donna S., Method for fabricating last level copper-to-C4 connection with interfacial cap structure.
  10. Lopatin,Sergey; Shanmugasundram,Arulkumar; Lubomirsky,Dmitry; Pancham,Ian A., Method for forming CoWRe alloys by electroless deposition.
  11. Su,Jiannong; Yang,Simon Shi ning; Zhang,Jian, Method for processing IC designs for different metal BEOL processes.
  12. Su,Jiannong; Yang,Simon Shi ning; Zhang,Jian, Method for using a Cu BEOL process to fabricate an integrated circuit (IC) originally having an al design.
  13. Edelstein, Daniel C.; Kang, Sung Kwon; McGlashan-Powell, Maurice; O'Sullivan, Eugene J.; Walker, George F., Method to selectively cap interconnects with indium or tin bronzes and/or oxides thereof and the interconnect so capped.
  14. Ivanov, Igor C.; Zhang, Weiguo, Methods and systems for processing a microelectronic topography.
  15. Chiang, Tony P.; Lazovsky, David E.; Boussie, Thomas R.; Gorer, Alexander, Methods for discretized processing of regions of a substrate.
  16. Lazovsky,David E.; Chiang,Tony P.; Keshavarz,Majid, Molecular self-assembly in substrate processing.
  17. Lubomirsky, Dmitry; Weidman, Timothy W.; Shanmugasundram, Arulkumar; Kovarsky, Nicolay Y.; Wijekoon, Kapila, Process for electroless copper deposition.
  18. Chiang, Tony P.; Lazovsky, David E.; Malhotra, Sandra G., Processing substrates using site-isolated processing.
  19. Weidman,Timothy W., Ruthenium containing layer deposition method.
  20. Farkas, Janos; Calvo-Munoz, Maria Luisa; Kordic, Srdjan, Semiconductor device including a coupled dielectric layer and metal layer, method of fabrication thereof, and passivating coupling material comprising multiple organic components for use in a semiconductor device.
  21. Lopatin,Sergey D.; Shanmugasundrum,Arulkumar; Shacham Diamand,Yosef, Silver under-layers for electroless cobalt alloys.
  22. Fresco, Zachary; Lang, Chi-I; Malhotra, Sandra G.; Chiang, Tony P.; Boussie, Thomas R.; Kumar, Nitin; Tong, Jinhong; Duong, Anh, Substrate processing including a masking layer.
  23. Wang,Xinming; Takagi,Daisuke; Tashiro,Akihiko; Fukunaga,Akira, Substrate processing method.
  24. Weiner, Kurt H.; Chiang, Tony P.; Pinto, Gustavo A., System and method for increasing productivity of combinatorial screening.
  25. Chiang, Tony P.; Lazovsky, David E.; Boussie, Thomas R.; McWaid, Thomas H.; Gorer, Alexander, Systems for discretized processing of regions of a substrate.
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