IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0651471
(2000-08-30)
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발명자
/ 주소 |
- Ahn, Kie Y.
- Forbes, Leonard
- Farrar, Paul A.
|
출원인 / 주소 |
|
대리인 / 주소 |
Schwegman, Lundberg, Woessner & Kluth, P.A.
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인용정보 |
피인용 횟수 :
11 인용 특허 :
85 |
초록
▼
A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with metal wires. Making the metal wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with metal to form th
A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with metal wires. Making the metal wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with metal to form the wires. Trench digging is time consuming and costly. Accordingly, the invention provides a new "trench-less" or "self-planarizing" method of making coplanar metal wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts aluminum or an aluminum alloy with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with aluminum to form a metallic wire coplanar with the first layer. Another step removes germanium oxide from the oxidized region to form a porous insulation having a very low dielectric constant, thereby reducing capacitance. Thus, the present invention not only eliminates the timing-consuming, trench-digging step of conventional methods, but also reduces capacitance which, in turn, enables faster, more-efficient integrated circuits.
대표청구항
▼
A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with metal wires. Making the metal wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with metal to form th
A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with metal wires. Making the metal wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with metal to form the wires. Trench digging is time consuming and costly. Accordingly, the invention provides a new "trench-less" or "self-planarizing" method of making coplanar metal wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts aluminum or an aluminum alloy with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with aluminum to form a metallic wire coplanar with the first layer. Another step removes germanium oxide from the oxidized region to form a porous insulation having a very low dielectric constant, thereby reducing capacitance. Thus, the present invention not only eliminates the timing-consuming, trench-digging step of conventional methods, but also reduces capacitance which, in turn, enables faster, more-efficient integrated circuits. rmed on said first insulating layer and having a prescribed electrical resistance; a second insulating layer formed on said resistor layer; a plurality of wirings electrically connected, at positions spaced a part from each other on said resistor layer, to said resistor layer through holes formed in said second insulating layer; and a heat storage layer formed in the vicinity of said resistor layer for storing heat generated when a current flows in said resistor layer, wherein said first insulating layer or said second insulating layer has a thin film insulating layer portion that has a thinner thickness where said-first insulating layer or said second insulating layer contacts said resistor layer, and said heat storage layer contacts at least said thin film insulating layer portion. 3. The semiconductor device according to claim 2, wherein said first insulating layer is an LOCOS oxide film, and said thin film insulating layer portion is an underlying oxide film formed on the substrate when said LOCOS oxide film is formed. 4. The semiconductor device according to claim 1, wherein said heat storage layer is an impurity-diffused layer formed on a portion of the substrate facing said resistor layer, and at least one of said plurality of wirings is electrically connected to said impurity-diffused layer. 5. The semiconductor device according to claim 1, wherein said heat storage layer is a laminated film consisting of a polysilicon film and a silicide film. 6. The semiconductor device according to claim 5, wherein said laminated film consisting of a polysilicon film and a silicide film is formed on said resistor layer intervening said second insulating layer. 7. The semiconductor device according to claim 6, wherein a metal layer is formed on said laminated film consisting of a polysilicon film and a silicide film by opening said second insulating layer. 8. The semiconductor device according to claim 5, wherein said laminated film consisting of a polysilicon film and a silicide film is formed underneath said resistor layer intervening said first insulating layer. 9. The semiconductor device according to claim 8, further comprising an impurity-diffused layer formed on the substrate underneath said laminated film consisting of a polysilicon film and a silicide film, wherein at least one of said plurality of wirings is electrically connected to said impurity-diffused layer. 10. The semiconductor device according to claim 3, wherein said heat storage layer is an impurity-diffused layer formed on a portion of the substrate facing said resistor layer, and at least one of said plurality of wirings is electrically connected to said impurity-diffused layer. 11. The semiconductor device according to claim 3, wherein said heat storage layer is a laminated film consisting of a polysilicon film and a silicide film. 12. The semiconductor device according to claim 11, wherein said laminated film consisting of a polysilicon film and a silicide film is formed on said resistor layer intervening said second insulating layer. 13. The semiconductor device according to claim 12, wherein a metal layer is formed on said laminated film consisting of a polysilicon film and a silicide film by opening said second insulating layer. 14. The semiconductor device according to claim 11, wherein said laminated film consisting of a polysilicon film and a silicide film is formed underneath said resistor layer intervening said first insulating layer. 15. The semiconductor device according to claim 14, further comprising an impurity-diffused layer formed on the substrate underneath said laminated film consisting of a polysilicon film and a silicide film, wherein at least one of said plurality of wirings is electrically connected to said impurity-diffused layer. 16. The semiconductor device according to claim 2, wherein said heat storage layer is an impurity-diffused layer formed on a portion of the substrate facing said resistor layer, and at least one
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