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A stator core assembly comprising adjacent packages of stacked lamination sheets that are separated by a plurality of radially extending spacer blocks, and each adjacent pair of spacer blocks define in cooperation with adjacent axially spaced laminations, a plurality of radial cooling ducts, each du

A stator core assembly comprising adjacent packages of stacked lamination sheets that are separated by a plurality of radially extending spacer blocks, and each adjacent pair of spacer blocks define in cooperation with adjacent axially spaced laminations, a plurality of radial cooling ducts, each duct having a least one lamination surface having plurality of concavities.

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A stator core assembly comprising adjacent packages of stacked lamination sheets that are separated by a plurality of radially extending spacer blocks, and each adjacent pair of spacer blocks define in cooperation with adjacent axially spaced laminations, a plurality of radial cooling ducts, each du

A stator core assembly comprising adjacent packages of stacked lamination sheets that are separated by a plurality of radially extending spacer blocks, and each adjacent pair of spacer blocks define in cooperation with adjacent axially spaced laminations, a plurality of radial cooling ducts, each duct having a least one lamination surface having plurality of concavities. aid plurality of metal lines and said metal interconnect lines. 3. The integrated circuit device of claim 2 wherein said plurality of metal lines extend at an angle of approximately 90 degrees relative to said metal interconnect lines. 4. The integrated circuit device of claim 1 wherein said low dielectric constant material comprises a dielectric constant of between about 2 and about 5. 5. The integrated circuit device of claim 4 wherein said high dielectric constant material has a dielectric constant of between about 6 and about 8. 6. The integrated circuit device of claim 4 wherein said high dielectric constant material has a dielectric constant of between about 6 and about 8. 7. The integrated circuit device of claim 4 wherein said passivation layer has a dielectric constant that is higher than said low dielectric constant material. 8. The integrated circuit device as described in claim 7 and further comprising: a silicon substrate; a boron phosphorus doped glass oxide extending over said substrate; a plurality of metal lines extending over said boron phosphorus doped glass oxide; and an oxide layer between said plurality of metal lines and said metal interconnect lines. 9. The integrated circuit device of claim 8 wherein said plurality of metal lines extend at an angle of approximately 90 degrees relative to said metal interconnect lines. 10. The integrated circuit device of claim 7 wherein said high dielectric constant material has a dielectric constant of between about 6 and about 8. 11. The integrated circuit device of claim 9 wherein said high dielectric constant material has a dielectric constant of between about 6 and about 8. 12. The integrated circuit device of claim 7 wherein said passivation layer has a dielectric constant that is higher than said low dielectric constant material. 13. An integrated circuit device comprising: a silicon substrate; a plurality of metal lines extending over said substrate; a plurality of top layer metal interconnect lines extending at an angle of approximately 90 degrees relative to said metal lines extending over said substrate; an oxide layer between said plurality of metal lines and said metal interconnect lines; a passivation layer disposed over said top layer metal interconnect lines and having gaps which extend between said metal interconnect lines; low dielectric constant material disposed over said passivation layer and in said gaps to prevent the deposition of a high dielectric constant material in said gaps and to reduce crosstalk between said metal interconnect lines at high operating speeds of said integrated circuit; high dielectric constant material disposed over said low dielectric constant material; and wherein said low dielectric constant material comprises polytetrafluoroethylene. 14. An integrated circuit device comprising: a wafer; plurality of metal lines extending over said wafer; a plurality of top layer metal interconnect lines extending at an angle of approximately 90 degrees relative to said metal lines extending over said substrate; an oxide layer between said plurality of metal lines and said metal interconnect lines; a passivation layer disposed over said top layer metal interconnect lines and having gaps which extend between said metal interconnect lines; low dielectric constant material disposed over said passivation layer and in said gaps to prevent the deposition of a high dielectric constant material in said gaps and to reduce crosstalk between said metal interconnect lines at high operating speeds of said integrated circuit; high dielectric constant material disposed over said low dielectric constant material; wherein said low dielectric constant material is cured by heating in an atmosphere selected from the group consisting of air, oxygen, argon, nitrogen, or forming gas; wherein said low dielectric constant material is cured at a temperature between about 100 degrees Celsius and about 500 degrees Celsius; wherein