IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0085315
(2002-02-28)
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발명자
/ 주소 |
- Drube, Thomas K.
- Emmer, Claus
- Bostrom, Brian
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
7 인용 특허 :
7 |
초록
▼
In a system for detecting overflow of a liquid cryogen storage tank, a differential pressure gauge measures the pressure of the tank at the top and bottom of the tank while liquid cryogen is introduced into the tank. Once the measurement reaches a predetermined amount, the operator terminates the fi
In a system for detecting overflow of a liquid cryogen storage tank, a differential pressure gauge measures the pressure of the tank at the top and bottom of the tank while liquid cryogen is introduced into the tank. Once the measurement reaches a predetermined amount, the operator terminates the fill. Alternatively, the differential pressure gauge sends a signal to the controller and the controller shuts the valves off. The tank includes an outlet pipe connected to either an audible device or avisual device and a vent stack. The excess cryogen, liquid or vapor, flows out of the tank through the outlet pipe. The audible device whistles when vapor passes through but is silent when the liquid passes through the audible device. This audible device provides a back-up warning which signifies when liquid cryogen is flowing out of the tank so that the operator may shut off the valves.
대표청구항
▼
In a system for detecting overflow of a liquid cryogen storage tank, a differential pressure gauge measures the pressure of the tank at the top and bottom of the tank while liquid cryogen is introduced into the tank. Once the measurement reaches a predetermined amount, the operator terminates the fi
In a system for detecting overflow of a liquid cryogen storage tank, a differential pressure gauge measures the pressure of the tank at the top and bottom of the tank while liquid cryogen is introduced into the tank. Once the measurement reaches a predetermined amount, the operator terminates the fill. Alternatively, the differential pressure gauge sends a signal to the controller and the controller shuts the valves off. The tank includes an outlet pipe connected to either an audible device or avisual device and a vent stack. The excess cryogen, liquid or vapor, flows out of the tank through the outlet pipe. The audible device whistles when vapor passes through but is silent when the liquid passes through the audible device. This audible device provides a back-up warning which signifies when liquid cryogen is flowing out of the tank so that the operator may shut off the valves. irst input coupled to receive the primary data bit from an associated primary memory device, the second input coupled to receive the redundant data bit from the redundant memory device, and the output configured to output either the primary data bit from the associated primary memory device or the redundant data bit responsive to a select signal provided to the select input; (ii) a store multiplexer including a plurality of data inputs, a select input and an output, the output coupled to the data line from the redundant memory device, and the plurality of data inputs configured to receive a plurality of primary data bits forming a data word to be stored in the memory array; and (iii) selection logic coupled to the select inputs of the fetch and store multiplexers, the selection logic responsive to redundant bit steering information to drive the select input of the store multiplexer to control the store multiplexer to output the primary data bit associated with the failed memory device to the redundant memory device. 4. The apparatus of claim 3, wherein the selection logic is further responsive to an initialization indicator that indicates whether the redundant memory device is being initialized, wherein, when the initialization indicator indicates that the redundant memory device is being initialized, the selection logic is configured to drive the select input of each of the fetch multiplexers to control each fetch multiplexer to output the primary data bit from the associated primary memory device, and when the initialization indicator indicates that the redundant memory device is not being initialized, the selection logic is responsive to the redundant bit steering information to drive the select input of the fetch multiplexer associated with the failed memory device to control such fetch multiplexer to output the redundant data bit in lieu of the primary data bit associated with the failed memory device. 5. The apparatus of claim 4, wherein the memory controller further includes a redundant bit steering array including a plurality of entries, each entry associated with one of a plurality of extents defined in the memory array, and each entry storing an initialization indicator and redundant bit steering information for the associated extent. 6. The apparatus of claim 4, wherein the memory controller further includes: (a) error correction logic coupled to the outputs of the fetch multiplexers, the error correction logic configured to generate a corrected fetch data word from the data bits output from the fetch multiplexers; and (b) error recovery code generation logic configured to receive a store data word and generate therefrom an error recovery code, the error recovery code generation logic configured to output the store data word and the error recovery code to both the memory array and the store multiplexer. 7. The apparatus of claim 6, wherein the memory controller further includes initialization logic coupled to the selection logic and the memory array, the initialization logic configured to, responsive to detection of a failure in a primary memory device, generate redundant bit steering information identifying the failed memory device, assert the initialization indicator, initiate a plurality of fetch and store operations associated with the failed memory device to copy data from the failed memory device to the redundant memory device, and thereafter deassert the initialization indicator. 8. The apparatus of claim 1, wherein the memory controller is configured to direct any non-initialization fetch operations associated with the failed memory device to the failed memory device, and direct any non-initialization store operations associated with the failed memory device to the redundant memory device, during processing of the initialization operation. 9. A circuit arrangement for use in controlling a memory array including a plurality of memory devices, the circuit arrangement configured to initialize a redun
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