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Method of making a semiconductor device using a silicon carbide hard mask 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/26
출원번호 US-0871546 (2001-05-30)
발명자 / 주소
  • Andideh, Ebrahim
출원인 / 주소
  • Intel Corporation
대리인 / 주소
    Seeley, Mark V.
인용정보 피인용 횟수 : 65  인용 특허 : 8

초록

A method of converting a hydrophobic surface of a silicon carbide layer to a hydrophilic surface is described. That method comprises forming a silicon carbide containing layer on a substrate, then operating a PECVD reactor to generate a plasma that converts the surface of that layer from a hydrophob

대표청구항

1. A method of forming a semiconductor device comprising: forming on a substrate a silicon carbide containing layer; introducing into a plasma enhanced chemical vapor deposition reactor, which contains the substrate that is covered with the silicon carbide containing layer, a gas that is selecte

이 특허에 인용된 특허 (8)

  1. Arnold John W. (Rolla MO) Brewer Terry L. (Rolla MO) Punyakumleard Sumalee (Rolla MO), Anti-reflective coating.
  2. Wang Fei ; Singh Bhanwar ; Kai James K., Dual damascene process using sacrificial spin-on materials.
  3. Gutsche Martin ; Tobben Dirk, Dual damascene structure.
  4. Yau Leopoldo D. (Durham OR) Gasser ; Jr. Robert A. (Cornelius OR) Week ; Jr. Kenneth R. (Sherwood OR) Yu Jick M. (Beaverton OR) Chin David D. (Aloha OR), MOS rear end processing.
  5. Neng-Hui Yang TW; Ming-Sheng Yang TW, Method for depositing silicon carbide in semiconductor devices.
  6. Hussein Makarem A. ; Sivakumar Sam ; Davis Rick, Method for making integrated circuit having polymer interlayer dielectric.
  7. Gregg John N. ; Jackson Robert M., Multi-component mixtures for manufacture of semi-conductors.
  8. Meador Jim D. ; Shao Xie ; Krishnamurthy Vandana ; Murphy Earnest C. ; Flaim Tony D. ; Brewer Terry Lowell, Non-subliming mid-UV dyes and ultra-thin organic arcs having differential solubility.

이 특허를 인용한 특허 (65)

  1. Lindert, Nick; Cea, Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
  2. Doyle, Brian S.; Jin, Been-Yih; Kavalieros, Jack T.; Datta, Suman; Brask, Justin K.; Chau, Robert S., CMOS devices with a single work function gate electrode and method of fabrication.
  3. Varadarajan, Bhadri N.; Gong, Bo; Yuan, Guangbi; Gui, Zhe; Lai, Fengyuan, Densification of silicon carbide film using remote plasma treatment.
  4. Brask, Justin K.; Datta, Suman; Doczy, Mark L.; Blackwell, James M.; Metz, Matthew V.; Kavalieros, Jack T.; Chau, Robert S., Dielectric interface for group III-V semiconductor device.
  5. Yu, Yongsik; Subramonium, Pramod; Fang, Zhiyuan; Henri, Jon; Apen, Elizabeth; Vitkavage, Dan, Diffusion barrier and etch stop films.
  6. Radosavljevic, Marko; Datta, Suman; Doyle, Brian S.; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Majumdar, Amian; Chau, Robert S., Field effect transistor with metal source/drain regions.
  7. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  8. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  9. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
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  16. Rangarajan, Vishwanathan; Antonelli, George Andrew; Banerji, Ananda; Van Schravendijk, Bart, Hardmask materials.
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  18. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors.
  19. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  20. Yu, Yongsik; Billington, Karen; Tang, Xingyuan; Fu, Haiying; Carris, Michael; Crew, William, Low-K SiC copper diffusion barrier films.
  21. Yu, Yongsik; Gupta, Atul; Billington, Karen; Carris, Michael; Crew, William; Mountsier, Thomas W., Low-k b-doped SiC copper diffusion barrier films.
  22. Wu,Zhen Cheng; Jang,Syun Ming, Metal barrier integrity via use of a novel two step PVD-ALD deposition procedure.
  23. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  24. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  25. Brask,Justin K.; Doyle,Brian S.; Kavalleros,Jack; Doczy,Mark; Shah,Uday; Chau,Robert S., Method of forming a metal oxide dielectric.
  26. Brask, Justin K.; Doyle, Brian S.; Kavalieros, Jack; Doczy, Mark; Shah, Uday; Chau, Robert S., Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric material.
  27. Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Chau, Robert S., Method of patterning a film.
  28. Choi,Hok Kin; Meagley,Robert P., Method to assay sacrificial light absorbing materials and spin on glass materials for chemical origin of defectivity.
  29. Choi,Hok Kin; Meagley,Robert P., Method to assay sacrificial light absorbing materials and spin on glass materials for chemical origin of defectivity.
  30. Varadarajan, Bhadri N., Method to obtain SiC class of films of desired composition and film properties.
  31. Brask, Justin K.; Kavalieros, Jack; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S.; Doyle, Brian S., Methods for patterning a semiconductor film.
  32. Chattopadhyay, Kaushik; Fox, Keith; Mountsier, Tom; Wu, Hui-Jung; van Schravendijk, Bart; Branshaw, Kimberly, Methods for reducing UV and dielectric diffusion barrier interaction.
  33. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  34. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  35. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
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  37. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
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  39. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  40. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
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  43. Brask, Justin K.; Dovle, Brian S.; Kavalleros, Jack; Doczy, Mark; Shah, Uday; Chau, Robert S., Nonplanar transistors with metal gate electrodes.
  44. Antonelli, George Andrew; Hollister, Alice; Reddy, Sirish, Oxygen-containing ceramic hard masks and associated wet-cleans.
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  57. Yu, Yongsik; van Schravendijk, Bart J.; Shankar, Nagraj; Varadarajan, Bhadri N., Staircase encapsulation in 3D NAND fabrication.
  58. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
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