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Semiconductor/printed circuit board assembly 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/13
  • H01L-023/32
출원번호 US-0855731 (2001-05-15)
우선권정보 SG-200101609 (2001-03-15)
발명자 / 주소
  • Vaiyapuri, Venkateshwaran
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Killworth, Gottman, Hagan & Schaeff, L.L.P.
인용정보 피인용 횟수 : 34  인용 특허 : 31

초록

A computer system and a printed circuit board assembly are provided comprising first and second semiconductor dies and an intermediate substrate. The intermediate substrate is positioned between a first active surface of the first semiconductor die and a second active surface of the second semicondu

대표청구항

A computer system and a printed circuit board assembly are provided comprising first and second semiconductor dies and an intermediate substrate. The intermediate substrate is positioned between a first active surface of the first semiconductor die and a second active surface of the second semicondu

이 특허에 인용된 특허 (31)

  1. Akram Salman, Apparatus for packaging flip chip bare die on printed circuit boards.
  2. Kaul Sunil (Fremont CA) Laird Douglas A. (Los Gatos CA), Ball grid array packages for high speed applications.
  3. Hirakawa Tadashi,JPX, Ball grid array semiconductor package.
  4. Toy Hilton T. ; Bolde Lannie R. ; Covell ; II James H. ; Edwards David L. ; Goldmann Lewis S. ; Gruber Peter A., Cast metal seal for semiconductor substrates.
  5. Spielberger Richard K. ; Jensen Ronald J. ; Speerschneider Charles J., Chip stacking and capacitor mounting arrangement including spacers.
  6. Saito Yasuhito,JPX ; Maekawa Youko,JPX ; Yoshioka Shimpei,JPX, Circuit substrate shielding device.
  7. Wark James M., Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  8. Ference Thomas G. ; Howell Wayne J. ; Sprogis Edmund J., Dual chip with heat sink.
  9. Lin Paul T., Face-to-face (FTF) stacked assembly of substrate-on-bare-chip (SOBC) modules.
  10. Eng Kian Teng,SGX ; Chan Min Yu,SGX ; Goh Jing Sua,SGX ; Low Siu Waf,SGX, Flexible pin location integrated circuit package.
  11. Hinrichsmeyer Kurt (Sindelfingen DEX) Straehle Werner (Dettenhausen VT DEX) Kelley ; Jr. Gordon A. (Essex Junction VT) Noth Richard W. (Fairfax VT), Integrated semiconductor chip package.
  12. Akram Salman ; Brooks Jerry M., Method of constructing stacked packages.
  13. Akram Salman ; Brooks Jerry M., Method of constructing stacked packages.
  14. Akram Salman (Boise ID) Wood Alan G. (Boise ID) Farnworth Warren M. (Nampa ID), Method of producing a single piece package for semiconductor die.
  15. Miyoshi Tadayoshi,JPX, Mounting structure for a semiconductor circuit.
  16. Liu Hermen,TWX, Multi-chip semiconductor package.
  17. Vaiyapuri Venkateshwaran SG; Ji Cheng Yang SG, Multichip semiconductor assembly.
  18. Kinsman Larry (Boise ID), Packaging means for a semiconductor die having particular shelf structure.
  19. Kweon Young Do (Seoul KRX), Reduced noise semiconductor package stack.
  20. King Jerrold L. (Boise ID) Brooks Jerry M. (Caldwell ID), Semiconductor chip package.
  21. Murakami Gen,JPX ; Tsubosaki Kunihiro,JPX ; Ichitani Masahiro,JPX ; Nishi Kunihiko,JPX ; Anjoh Ichiro,JPX ; Nishimura Asao,JPX ; Kitano Makoto,JPX ; Yaguchi Akihiro,JPX ; Kawai Sueo,JPX ; Ogata Masat, Semiconductor device.
  22. Ano Kazuaki,JPX ; Murata Kensho,JPX, Semiconductor device and manufacturing method.
  23. Juso Hiroyuki,JPX ; Sota Yoshiki,JPX ; Maruyama Tomoyo,JPX, Semiconductor device having a plurality of semiconductor chips.
  24. Masayuki Watanabe,JPX ; Toshio Sugano,JPX ; Seiichiro Tsukui,JPX ; Takashi Ono,JPX ; Yoshiaki Wakashima,JPX, Semiconductor memory module having double-sided memory chip layout.
  25. Akram Salman ; Wood Alan G. ; Farnworth Warren M., Stackable chip scale semiconductor package with mating contacts on opposed surfaces.
  26. Akram Salman, Stacked leads-over-chip multi-chip module.
  27. Farnworth Warren M. ; Wood Alan G. ; Brooks Mike, Stacked semiconductor package and method of fabrication.
  28. Lin Paul T. (Austin TX) McShane Michael B. (Austin TX), Stacking three dimensional leadless multi-chip module and method for making the same.
  29. Baba Shinji,JPX ; Shibata Jun,JPX ; Ueda Tetsuya,JPX, Substrateless resin encapsulated semiconductor device.
  30. Degani Yinon (Highland Park NJ) Dudderar Thomas Dixon (Chatham NJ) Han Byung Joon (Scotch Plains NJ) Lyons Alan Michael (New Providence NJ), Thin packaging of multi-chip modules with enhanced thermal/power management.
  31. Weber Patrick O. (San Jose CA) Brueggeman Michael A. (Mountain View CA), Transfer modlded electronic package having a passage means.

이 특허를 인용한 특허 (34)

  1. Cole, Barrett E.; Marta, Terry, Beam intensity detection in a cavity ring down sensor.
  2. Cole, Barrett E., CRDS mirror for normal incidence fiber optic coupling.
  3. Cole, Barrett E., Cavity enhanced photo acoustic gas sensor.
  4. Cole, Barrett E., Cavity ring-down spectrometer having mirror isolation.
  5. Cox, James Allen; Cole, Barrett E., Compact gas sensor using high reflectance terahertz mirror and related system and method.
  6. Tago, Masamoto, Compact semiconductor device capable of mounting a plurality of semiconductor chips with high density and method of manufacturing the same.
  7. Tago,Masamoto, Compact semiconductor device capable of mounting a plurality of semiconductor chips with high density and method of manufacturing the same.
  8. Fritz, Bernard, Enhanced cavity for a photoacoustic gas sensor.
  9. Cox, James Allen; Higashi, Robert, High reflectance terahertz mirror and related method.
  10. Chen,Jian Cheng; Cheng,Ming Hsiang; Lee,Chia Jung, Image sensor module having an image signal processor being physically and electrically unconnected to a supporting board of an image sensor chip.
  11. Higashi, Robert E.; Newstrom-Peitso, Karen M.; Ridley, Jeffrey A., Integral topside vacuum package.
  12. Sutardja, Sehat, Integrated chip package having intermediate substrate.
  13. Sutardja,Sehat, Integrated chip package having intermediate substrate and multiple semiconductor chips.
  14. Sutardja, Sehat, Integrated chip package having intermediate substrate with capacitor.
  15. Sutardja, Sehat, Integrated chip package having intermediate substrate with capacitor.
  16. Fernandez,Elstan Anthony, Integrated circuit package employing a heat-spreader member.
  17. Connell, Mike; Jiang, Tongbi, Method for fabricating board on chip (BOC) semiconductor package with circuit side polymer layer.
  18. Connell,Mike; Jiang,Tongbi, Method for fabricating semiconductor package with circuit side polymer layer.
  19. Akram, Salman, Multi-chip module substrate for use with leads-over chip type semiconductor devices.
  20. Hsu, Chi-Hsing, Multi-chip package with embedded cooling element.
  21. Wang, Meng-Jen, Multi-chips stacked package.
  22. Cole,Barrett E.; Higashi,Robert E.; Zins,Christopher J.; Krishnankutty,Subash, Multi-substrate package assembly.
  23. Cole,Barrett E.; Higashi,Robert E.; Zins,Christopher J.; Krishnankutty,Subash, Multi-substrate package assembly.
  24. Cole, Barrett E.; Marta, Terry; Cox, James Allen; Nusseibeh, Fouad, Multiple wavelength cavity ring down gas sensor.
  25. Cole, Barrett E.; Cox, James A.; Zook, J. David, Optical cavity system having an orthogonal input.
  26. Chen, Meng-Tse; Lin, Wei-Hung; Wu, Sheng-Yu; Jang, Bor-Ping; Cheng, Ming-Da; Liu, Chung-Shi; Lin, Hsiu-Jen; Lu, Wen-Hsiung; Lin, Chih-Wei; Tsai, Yu-Peng; Huang, Kuei-Wei; Lin, Chun-Cheng, Package on-package process for applying molding compound.
  27. Chen, Meng-Tse; Lin, Wei-Hung; Wu, Sheng-Yu; Lin, Chun-Cheng; Huang, Kuei-Wei; Tsai, Yu-Peng; Lin, Chih-Wei; Lu, Wen-Hsiung; Lin, Hsiu-Jen; Jang, Bor-Ping; Cheng, Ming-Da; Liu, Chung-Shi, Package-on-package process for applying molding compound.
  28. Michii, Kazunari; Shibata, Jun, Semiconductor package including stacked semiconductor chips.
  29. Connell, Mike; Jiang, Tongbi, Semiconductor package with circuit side polymer layer and wafer level fabrication method.
  30. Connell,Mike; Jiang,Tongbi, Semiconductor package with circuit side polymer layer and wafer level fabrication method.
  31. Vaiyapuri, Venkateshwaran, Semiconductor/printed circuit board assembly, and computer system.
  32. Ellsberry,Mark; Schmitz,Charles E.; Chen,Chi She; Allison,Victor, Stackable electronic assembly.
  33. Connell, Mike; Jiang, Tongbi, Stacked semiconductor package with circuit side polymer layer.
  34. Hsu,Shih Ping, Surface structure of flip chip substrate.
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