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An electronic equipment enclosure (10) for housing electronic equipment (11), and broadly comprising a pivot bracket (22); a plurality of sleeves (24), each being associated with a transmit terminal (26), a receive terminal (28), protective circuitry (30), and test circuitry (32); a spreader plate (

An electronic equipment enclosure (10) for housing electronic equipment (11), and broadly comprising a pivot bracket (22); a plurality of sleeves (24), each being associated with a transmit terminal (26), a receive terminal (28), protective circuitry (30), and test circuitry (32); a spreader plate (38); and a heat sink (40). The pivot bracket (22) allows for tilting an outer housing (12) up to 30° relative to a mounting surface. The separate and distinct transmit and receive terminals (26,28) maintain minimum cross-talk and interference levels. The protective and the test circuitries (30,32) are located on daughter boards adjacent each sleeve (24) so as to be easily accessible. The spreader plate (38) is operable to force the sleeves (24) into direct contact with the interior surface of the outer housing (18). The heat sink (40) is operable to facilitate conductive heat transfer between the sleeves (24) and the lid (18).

대표청구항 ▼

An electronic equipment enclosure (10) for housing electronic equipment (11), and broadly comprising a pivot bracket (22); a plurality of sleeves (24), each being associated with a transmit terminal (26), a receive terminal (28), protective circuitry (30), and test circuitry (32); a spreader plate (

An electronic equipment enclosure (10) for housing electronic equipment (11), and broadly comprising a pivot bracket (22); a plurality of sleeves (24), each being associated with a transmit terminal (26), a receive terminal (28), protective circuitry (30), and test circuitry (32); a spreader plate (38); and a heat sink (40). The pivot bracket (22) allows for tilting an outer housing (12) up to 30° relative to a mounting surface. The separate and distinct transmit and receive terminals (26,28) maintain minimum cross-talk and interference levels. The protective and the test circuitries (30,32) are located on daughter boards adjacent each sleeve (24) so as to be easily accessible. The spreader plate (38) is operable to force the sleeves (24) into direct contact with the interior surface of the outer housing (18). The heat sink (40) is operable to facilitate conductive heat transfer between the sleeves (24) and the lid (18). eby reducing the electrostatic charges on the patterned photoresist; and evaluating the patterned photoresist with an electron beam. Another aspect of the present invention relates to a system for reducing electrostatic charges on a patterned photoresist, containing a charge sensor for determining if electrostatic charges exist on the patterned photoresist and measuring the electrostatic charges; an ionizer positioned near the patterned photoresist having electrostatic charges thereon for reducing the electrostatic charges on the patterned photoresist; a controller for setting at least one of time of ion generation and amount of ion generation by the ionizer, the controller coupled to the charge sensor and the ionizer; and a scanning electron microscope or an atomic force microscope for evaluating the patterned photoresist having reduced electrostatic charges thereon with an electron beam. exceeds the supply voltage. 4. The electrostatic protection circuit according to claim 3, wherein the first resistor is a second nMOSFET set to an off state. 5. The electrostatic protection circuit according to claim 2, further comprising a second resistor connected in parallel with the first diode array between the gate of the first nMOSFET and the input/output terminal. 6. The electrostatic protection circuit according to claim 5, wherein: a value of the first resistor and a value of the second resistor are set so that the first nMOSFET is off when a voltage at the input/output terminal is between the ground potential and a supply voltage; and a number of diodes comprising the first diode array and a value of the first resistor are set so that the first nMOSFET is on when the voltage at the input/output terminal exceeds the supply voltage. 7. The electrostatic protection circuit according to claim 6, wherein: the first resistor is a second nMOSFET set to an off state; and the second resistor is a third nMOSFET set to an off state. 8. The electrostatic protection circuit according to claim 5, further comprising: a second protection MOSFET comprising a drain connected to the input/output terminal, a source and a substrate connected to a supply voltage; a second diode array comprising at least one diode and connected in series in a forward direction between a gate of the second protection MOSFET and the input/output terminal; a third resistor connected between the gate of the second protection MOSFET and the supply voltage; and a fourth resistor connected in parallel with the second diode array between the gate of the second protection MOSFET and the input/output terminal. 9. The electrostatic protection circuit according to claim 8, wherein the second protection MOSFET is a first pMOSFET. 10. The electrostatic protection circuit according to claim 9, wherein: a value of the first resistor and a value of the second resistor are set so that the first nMOSFET is off when a voltage at the input/output terminal is between the ground potential and the supply voltage; a number of diodes comprising the first diode array and a value of the first resistor are set so that the first nMOSFET is on when the voltage of the input/output terminal exceeds the supply voltage; a value of the third resistor and a value of the fourth resistor are set so that the first pMOSFET is off when the voltage at the input/output terminal is between the ground potential and the supply voltage; and a number of diodes comprising the second diode array and the value of the third resistor are set so that the first pMOSFET is on when the voltage at the input/output terminal is less than the ground potential. 11. The electrostatic protection circuit according to claim 10, wherein: the first resistor is a second nMOSFET set to an off state; the second resistor is a third nMOSFET set to an off state; the third resistor is a second pMOSFET set to an off state; and the fourth resistor is a third pMOSFET set to an off state. 12. The electrostatic protection circuit according to claim 2, further comprising: a second protection MOSFET comprising a drain connected to the input/output terminal, and a source and a substrate connected to a supply voltage; a second diode array comprising at least one diode and connected in series in a forward direction between a gate of the second protection MOSFET and the input/output terminal; and a second resistor connected between the gate of the second protection MOSFET and the supply voltage. 13. The electrostatic protection circuit according to claim 12, wherein the second protection MOSFET is a first pMOSFET. 14. The electrostatic protection circuit according to claim 13, wherein: a number of diodes comprising the first diode array and a value of the first resistor are set so that the first nMOSFET is off when a voltage at the input/output terminal is between the ground potential and a supp ly voltage, and the first nMOSFET is on when a voltage at the input/output terminal exceeds the supply voltage; and a number of diodes comprising in the second diode array and a value of the second resistor are set so that the first pMOSFET is off when the voltage at the input/output terminal is between the ground potential and the supply voltage, and the first pMOSFET is on when the voltage at the input/output terminal is less than the ground potential. 15. The electrostatic protection circuit according to claim 13, wherein: the first resistor is a second nMOSFET set to an off state; and the second resistor is a third nMOSFET set to an off state. 16. The electrostatic protection circuit according to claim 1, wherein the first protection MOSFET is a first pMOSFET and the predetermined voltage is a supply voltage. 17. The electrostatic protection circuit according to claim 16, wherein a number of diodes comprising the first diode array and a value of the first resistor are set so that the first pMOSFET is off when a voltage at the input/output terminal is between ground potential and the supply voltage, and the first pMOSFET is on when the voltage at the input/output terminal is less than the ground potential. 18. The electrostatic protection circuit according to claim 17, wherein the first resistor is a second pMOSFET set to an off state. 19. The electrostatic protection circuit according to claim 16, further comprising a second resistor connected in parallel with the first diode array between the gate of the first pMOSFET and the input/output terminal. 20. The electrostatic protection circuit according to claim 19, wherein: a value of the first resistor and a value of the second resistor are set so that the first pMOSFET is off when a voltage at the input/output terminal is between a ground potential and the supply voltage; and a number of diodes comprising the first diode array and a value of the first resistor are set so that the first pMOSFET is on when the voltage of the input/output terminal is less than the ground potential. 21. The electrostatic protection circuit according to claim 19, wherein: the first resistor is a second pMOSFET set to an off state; and the second resistor is a third pMOSFET set to an off state. 22. The electrostatic protection circuit according to claim 16, further comprising: a second protection MOSFET comprising a drain connected to the input/output terminal and a source and a substrate connected to a ground potential; a second diode array comprising at least one diode and connected in series in a forward direction between a gate of the second protection MOSFET and the input/output terminal; a third resistor connected in parallel with the second diode array between the gate of the second protection MOSFET and the input/output terminal; and a fourth resistor connected between the gate of the second protection MOSFET and a ground potential. 23. An electrostatic protection circuit, comprising: a protection MOSFET comprising a drain connected to an input/output terminal, and a source and a gate connected to a predetermined voltage; a diode array comprising at least one diode and connected in series in a forward direction between a substrate of the protection MOSFET and the input/output terminal; and a resistor connected between the substrate of the protection MOSFET and a ground potential. 24. The electrostatic protection circuit according to claim 23, wherein the protection MOSFET is a protection nMOSFET, and the predetermined voltage is a ground potential. 25. The electrostatic protection circuit according to claim 23, wherein the protection MOSFET is a protection pMOSFET, and the predetermined voltage is a supply voltage. 26. An electrostatic protection circuit, comprising: a first protection MOSFET comprising a drain connected to an input/output terminal, and a source and a gate connected to a predetermined voltage source; a first diode array co mprising at least one diode and connected in series in a forward direction between a substrate of the first protection MOSFET and the input/output terminal; and a first resistor connected between the substrate of the first protection MOSFET and the predetermined voltage source. 27. The electrostatic protection circuit according to claim 26, wherein the first protection MOSFET is a first nMOSFET, and the predetermined voltage source is a ground potential. 28. The electrostatic protection circuit according to claim 27, wherein a number of diodes comprising the first diode array and a value of the first resistor are set, so that the first nMOSFET is off when a voltage at the input/output terminal is between the ground potential and a supply voltage, and a current flows from the substrate of the first nMOSFET to the source of the first nMOSFET when the voltage at the input/output terminal exceeds the supply voltage. 29. The electrostatic protection circuit according to claim 28, wherein the first resistor is a second nMOSFET set to an off state. 30. The electrostatic protection circuit according to claim 27, further comprising a second resistor connected in parallel with the first diode array between the substrate of the first nMOSFET and the input/output terminal. 31. The electrostatic protection circuit according to claim 30, wherein: a value of the first resistor and a value of the second resistor are set so that the first nMOSFET is off when a voltage at the input/output terminal is between the ground potential and a supply voltage; and a number of diodes comprising the first diode array and a value of the first resistor are set so that a current flows from the substrate of the first nMOSFET to the source of the first nMOSFET when the voltage at the input/output terminal exceeds the supply voltage. 32. The electrostatic protection circuit according to claim 31, wherein: the first resistor is a second nMOSFET set to an off state; and the second resistor is a third nMOSFET set to an off state. 33. The electrostatic protection circuit according to claim 30, further comprising: a second protection MOSFET comprising a drain connected to the input/output terminal, a source and a gate connected to a supply voltage; a second diode array comprising at least one diode and connected in series in a forward direction between a substrate of the second protection MOSFET and the input/output terminal; a third resistor connected between the substrate of the second protection MOSFET and the supply voltage; and a fourth resistor connected in parallel with the second diode array between the substrate of the second protection MOSFET and the input/output terminal. 34. The electrostatic protection circuit according to claim 33, wherein the second protection MOSFET is a first pMOSFET. 35. The electrostatic protection circuit according to claim 34, wherein: a value of the first resistor and a value of the second resistor are set so that the first nMOSFET is off when a voltage at the input/output terminal is between the ground potential and the supply voltage; a number of diodes comprising the first diode array and a value of the first resistor are set so that a current flows from the substrate of the first nMOSFET to the source of the first nMOSFET when the voltage of the input/output terminal exceeds the supply voltage; a value of the third resistor and a value of the fourth resistor are set so that the first pMOSFET is off when the voltage at the input/output terminal is between the ground potential and the supply voltage; and a number of diodes comprising the second diode array and the value of the third resistor are set so that the a current flows from the source of the first pMOSFET to the substrate of the first pMOSFET when the voltage at the input/output terminal is less than the ground potential. 36. The electrostatic protection circuit according to claim 35, wherein: the first resistor is a second nMOSFET set