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A compressor stator includes an outer casing supporting a row of stator vanes extending radially inwardly therefrom. Each vane includes pressure and suction sides extending axially between leading and trailing edges and radially between a root and a tip. The root and tip are twisted relative to a pi

A compressor stator includes an outer casing supporting a row of stator vanes extending radially inwardly therefrom. Each vane includes pressure and suction sides extending axially between leading and trailing edges and radially between a root and a tip. The root and tip are twisted relative to a pitch section disposed therebetween. Each vane tip is radially convex adjacent a leading edge for defining an axially concave outer flowpath in the casing for reducing peak velocity of airflow for enhanced efficiency.

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A compressor stator includes an outer casing supporting a row of stator vanes extending radially inwardly therefrom. Each vane includes pressure and suction sides extending axially between leading and trailing edges and radially between a root and a tip. The root and tip are twisted relative to a pi

A compressor stator includes an outer casing supporting a row of stator vanes extending radially inwardly therefrom. Each vane includes pressure and suction sides extending axially between leading and trailing edges and radially between a root and a tip. The root and tip are twisted relative to a pitch section disposed therebetween. Each vane tip is radially convex adjacent a leading edge for defining an axially concave outer flowpath in the casing for reducing peak velocity of airflow for enhanced efficiency. of the pixels including the row of the dummy pixels. 14. A solid-state imaging device comprising: an image section comprising a matrix of pixels and a row of dummy pixels; a vertical register circuit configured to drive a row of pixels; a horizontal register circuit configured to select a column of pixels; and a timing generator configured to supply a signal charge time control signal to said vertical register circuit, wherein said vertical register circuit is configured to drive rows of the pixels in the matrix and the row of the dummy pixels successively, and said timing generator changes a signal storage timing within one field period at intervals of one field. 15. A solid-state imaging device comprising: an image section comprising a matrix of pixels and a row of dummy pixels; a vertical register circuit configured to drive a row of pixels; a horizontal register circuit configured to select a column of pixels; and a timing generator configured to supply a signal charge time control signal to said vertical register circuit, wherein said vertical register circuit is configured to drive rows of the pixels in the matrix and the row of the dummy pixels successively, and said timing generator controls the vertical register circuit with a signal storage timing made relatively different from a signal read timing. 16. A solid-state imaging device comprising: an image section comprising a matrix of pixels and a row of dummy pixels; a vertical register circuit configured to drive a row of pixels; a horizontal register circuit configured to select a column of pixels; and a timing generator configured to supply a signal charge time control signal to said vertical register circuit, wherein said vertical register circuit is configured to drive rows of the pixels in the matrix and the row of the dummy pixels successively, and said vertical register circuit comprises: a read-out vertical shift register configured to control a start time at which an image signal is read out from the matrix of the pixels; a first electronic shutter vertical shift register configured to control a start time of a signal storage in the matrix of the pixels in a first field period; and a second electronic shutter vertical shift register configured to control a start time of the signal storage in the matrix of the pixels in a second field period alternated with the first field period. 17. A solid-state imaging device comprising: an image section comprising a matrix of pixels and a row of dummy pixels; a vertical register circuit configured to drive a row of pixels; a horizontal register circuit configured to select a column of pixels; and a timing generator configured to supply a signal charge time control signal to said vertical register circuit, wherein said vertical register circuit is configured to drive rows of the pixels in the matrix and the row of the dummy pixels successively, and said timing generator controls the vertical register circuit in such a manner that, when each row of pixels in an imaging area is driven twice with a signal storage timing and with a signal read timing, a voltage of another line adjacent to each read line is substantially equal when driven twice. 18. The solid-state imaging device according to claim 17, wherein the another line is one of vertical