초록 ▼

A method and apparatus for developing run-time parameterizable logic cores for programmable logic devices (PLDs). In various embodiments, logic cores are defined in a run-time reconfiguration program, the logic cores having output pins and input pins. A pre-route tool routes selected ones of the out

A method and apparatus for developing run-time parameterizable logic cores for programmable logic devices (PLDs). In various embodiments, logic cores are defined in a run-time reconfiguration program, the logic cores having output pins and input pins. A pre-route tool routes selected ones of the output pins to selected ones of the input pins and generates program code for the run-time reconfiguration program. The program code generated by the pre-route tool programs interconnect resources that make the required connections. The automatically generated program code is then parameterized and included in the run-time reconfiguration program.

대표청구항 ▼

A method and apparatus for developing run-time parameterizable logic cores for programmable logic devices (PLDs). In various embodiments, logic cores are defined in a run-time reconfiguration program, the logic cores having output pins and input pins. A pre-route tool routes selected ones of the out

A method and apparatus for developing run-time parameterizable logic cores for programmable logic devices (PLDs). In various embodiments, logic cores are defined in a run-time reconfiguration program, the logic cores having output pins and input pins. A pre-route tool routes selected ones of the output pins to selected ones of the input pins and generates program code for the run-time reconfiguration program. The program code generated by the pre-route tool programs interconnect resources that make the required connections. The automatically generated program code is then parameterized and included in the run-time reconfiguration program. a second signal indicative of the presence or absence of the second error; and a corrector for alternatively receiving the first and second data groups, the corrector correcting the first error in the first data group responsive to the first signal indicative of the presence or absence of the first error and the second error in the second data group responsive to the second signal indicative of the presence or absence of the second error. 2. The semiconductor memory device of claim 1 wherein the corrected data bits of the first and the second group are alternatively externally provided through the input/output circuit. 3. A semiconductor memory device, comprising: a memory cell array for storing a plurality of data bits and a plurality of check bits corresponding to the plurality of data bits, the plurality of data bits being divided into at least a first and a second data groups and the plurality of check bits being divided into at least first and second check bit groups; a read circuit for reading out the plurality of data bits and the plurality of check bits from the memory cell array; an input/output circuit for externally inputting/outputting the plurality of data bits and the plurality of check bits; a first syndrome generator for sequentially receiving the first data group and the first check bit group and generating first syndrome bits responsive thereto; a second syndrome generator for sequentially receiving the first data group and the first check bit group and generating second syndrome bits responsive thereto substantially simultaneously as the first syndrome generator sequentially receives the first data group and the first check bit group; a detector for alternatively receiving the first and the second syndrome bits from the first and the second syndrome generator, decoding the first syndrome bits to detect the first error in the first data group and the second syndrome bits to detect the second error in the second data group, and generating a first signal indicative of the presence or absence of the first error and a second signal indicative of the presence or absence of the second error; and a corrector for alternatively receiving the first and second data groups, correcting the first error in the first data group responsive to the first signal indicative of the presence or absence of the first error and the second error in the second data group responsive to the second signal indicative of the presence or absence of the second error, wherein the first and second data groups respectively corrected by the corrector are alternatively externally provided through the input/output circuit. 4. A semiconductor memory device, comprising: a memory cell array divided into a plurality of input/output memory blocks, each of the input/output memory blocks storing a plurality of data bits and a plurality of check bits corresponding to the plurality of data bits; a plurality of input/output circuits corresponding to the plurality of the input/output memory blocks; a read circuit for reading out the plurality of data and check bits from each input/output memory block; means for correcting an error in the data bits read out from each input/output memory block comprising a plurality of error correction sections respectively corresponding to the input/output circuits, each of the error correction sections comprising a first error correction circuit for correcting a first error in odd-numbered data bits read out from a corresponding input/output memory block and a second error correction circuit for correcting a second error in even-numbered data bits read out from the corresponding input/output memory block; wherein the first error correction circuit comprises: a first syndrome generator for sequentially receiving odd-numbered data and check bits read out from the corresponding input/output memory block, to generate first syndrome bits responsive thereto; a first detector for decoding the first syndrome