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특허 상세정보

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High mobility FETS using A1203 as a gate oxide

특허상세정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) H01C-021/8242   
미국특허분류(USC) 438/240; 438/287; 438/785; 438/591; 438/624
출원번호 US-0888777 (2001-06-25)
발명자 / 주소
출원인 / 주소
대리인 / 주소
    Scully, Scott, Murphy & Presser
인용정보 피인용 횟수 : 43  인용 특허 : 5
초록

A method of forming a high-k dielectric material which exhibits a substantially lower amount of trap charge within a gate stack region is provided. The method maintains high-temperatures (250° C. or above) such that the substrate wafer is not cooled during the various processing steps. Such a method leads to the formation of a high-k dielectric material which does not exhibit a hysteric behavior in a capacitance-voltage curve as well as an increased mobility on FETs using conventional CMOS processing.

대표
청구항
▼

A method of forming a high-k dielectric material which exhibits a substantially lower amount of trap charge within a gate stack region is provided. The method maintains high-temperatures (250° C. or above) such that the substrate wafer is not cooled during the various processing steps. Such a method leads to the formation of a high-k dielectric material which does not exhibit a hysteric behavior in a capacitance-voltage curve as well as an increased mobility on FETs using conventional CMOS processing. stry, vol. 267, No. 17, Jun. 15, 1992, pp. 12244-1225...

이 특허에 인용된 특허 (5)

  1. Bakli Mouloud,FRX ; Ghanayem Steve G. ; Tran Huyen T.. Method of tantalum nitride deposition by tantalum oxide densification. USP2001116319766.
  2. Young-wook Park KR; Moon-yong Lee KR; Kyung-hun Kim KR; In-sung Park KR. Methods for forming films having high dielectric constants. USP2002076426308.
  3. Lee Seung-Hwan,KRX ; Lee Sang-Hyeop,KRX ; Kim Young-Sun,KRX ; Shim Se-Jin,KRX ; Jin You-Chan,KRX ; Moon Ju-Tae,KRX ; Choi Jin-Seok,KRX ; Kim Young-Min,KRX ; Kim Kyung-Hoon,KRX ; Nam Kab-Jin,KRX ; Par. Methods of forming integrated circuit capacitors having improved electrode and dielectric layer characteristics and capacitors formed thereby. USP2001046218260.
  4. Roeder Jeffrey ; Van Buskirk Peter C.. Process for controlled orientation of ferroelectric layers. USP1999125998236.
  5. Okada Yoshio (Austin TX) Tobin Philip J. (Austin TX). Process for fabricating a semiconductor device having a high reliability dielectric material. USP1995045407870.

이 특허를 인용한 특허 피인용횟수: 43

  1. Wang, Chang-Gong; Shero, Eric; Wilk, Glen. ALD of metal silicate films. USP2013108563444.
  2. Wang, Chang-Gong; Shero, Eric; Wilk, Glen. ALD of metal silicate films. USP2011077972977.
  3. Hattendorf, Michael L.; Brask, Justin K.; Sandford, Justin S.; Kavalieros, Jack; Metz, Matthew V.. Angled implantation for removal of thin film layers. USP2009097595248.
  4. Okura, Seiji; Suemori, Hidemi; Pore, Viljami J.. Deposition of titanium nanolaminates for use in integrated circuit fabrication. USP2017019540729.
  5. Wang, Chang-Gong; Shero, Eric. Doping with ALD technology. USP2015099139906.
  6. Cheng, Kangguo; Khakifirooz, Ali; Ponoth, Shom; Sreenivasan, Raghavasimhan. Dual epitaxy region integration. USP2015129224607.
  7. Adusumilli, Praneet; Callegari, Alessandro; Chang, Josephine B.; Choi, Changhwan; Frank, Martin Michael; Guillorn, Michael A.; Narayanan, Vijay. Field-effect transistor device having a metal gate stack with an oxygen barrier layer. USP2013048415677.
  8. Rotondaro, Antonio L. P.; Colombo, Luigi; Visokay, Mark R.; Khamankar, Rajesh; Mercer, Douglas E.. Gate structure and method. USP2009057535066.
  9. Rotondaro, Antonio L. P.; Colombo, Luigi; Visokay, Mark R; Khamankar, Rajesh; Mercer, Douglas E. Gate structure and method. USP2011098021990.
  10. Yu, Chen-Hua; Yao, Liang-Gi. High-k gate dielectric and method of manufacture. USP2012108294201.
  11. Yu, Chen-Hua; Yao, Liang-Gi. High-k gate dielectric and method of manufacture. USP2011087998820.
  12. Flynn,Jeffrey S.; Xin,Huoping; Brandes,George R.. III-nitride optoelectronic device structure with high Al AlGaN diffusion barrier. USP2007107282744.
  13. Chen, Tze-Chiang; Guo, Dechao; Oldiges, Philip J.; Wang, Yanfeng. Interface structure for channel mobility improvement in high-k metal gate stack. USP2013078492852.
  14. Guha, Supratik; Narayanan, Vijay; Paruchuri, Vamsi K.. Method and apparatus for flatband voltage tuning of high-k field effect transistors. USP2014028658501.
  15. Haukka, Suvi; Huotari, Hannu. Method of depositing barrier layer for metal gates. USP2005026858524.
  16. Huotari,Hannu; Haukka,Suvi; Tuominen,Marko. Method of forming an electrode with adjusted work function. USP2006057045406.
  17. Haukka, Suvi; Huotari, Hannu. Method of producing thin films. USP2009077563715.
  18. Huotari,Hannu. Method to fabricate dual metal CMOS devices. USP2006107122414.
  19. Pore, Viljami; Ritala, Mikko; Leskela, Markku. Methods for forming conductive titanium oxide thin films. USP2017059646820.
  20. Pore, Viljami; Ritala, Mikko; Leskelä, Markku. Methods for forming conductive titanium oxide thin films. USP2015028945675.
  21. Herbots, Nicole; Bradley, James; Shaw, Justin Maurice; Culbertson, Robert J.; Atluri, Vasudeva. Methods for preparing semiconductor substrates and interfacial oxides thereon. USP2010127851365.
  22. Herbots, Nicole; Whaley, Shawn; Culbertson, Robert; Bennett-Kennett, Ross; Murphy, Ashlee; Bade, Matthew; Farmer, Sam; Hudzietz, Brance. Methods for wafer bonding and for nucleating bonding nanophases using wet and steam pressurization. USP2017039589801.
  23. Herbots, Nichole; Bennett-Kennett, Ross; Murphy, Ashlee; Hughes, Brett; Acharya, Ajjya; Watson, Clarizza; Culbertson, Robert. Methods for wafer bonding, and for nucleating bonding nanophases. USP2016089418963.
  24. Herbots, Nicole; Culbertson, Robert J.; Bradley, James; Hart, Murdock Allen; Sell, David Alexander; Whaley, Shawn David. Methods for wafer bonding, and for nucleating bonding nanophases. USP2015049018077.
  25. Wang, Chih Hao; Wang, Ta Wei; Chen, Shang Chih; Tsai, Ching Wei. Nitrogen treatment to improve high-k gate dielectrics. USP2009077564108.
  26. Milligan, Robert B.; Li, Dong; Marcus, Steven. Plasma-enhanced atomic layer deposition of conductive material over dielectric layers. USP2016109466574.
  27. Milligan, Robert B.; Li, Doug; Marcus, Steven. Plasma-enhanced atomic layers deposition of conductive material over dielectric layers. USP2013108557702.
  28. Hareland,Scott A.; Lindert,Nick; Arghavani,Reza; Chau,Robert. Pre-etch implantation damage for the removal of thin film layers. USP2006057045073.
  29. Cheung, Fred TK; Halliyal, Arvind. Precision high-K intergate dielectric layer. USP2004066750066.
  30. Pore, Viljami J.; Okura, Seiji; Suemori, Hidemi. Process for deposition of titanium oxynitride for use in integrated circuit fabrication. USP20180610002755.
  31. Pore, Viljami J.; Okura, Seiji; Suemori, Hidemi. Process for deposition of titanium oxynitride for use in integrated circuit fabrication. USP2016129523148.
  32. Chiu,Hsien Kuang; Perng,Baw Ching; Tao,Hun Jan. Process for patterning high-k dielectric material. USP2006127148114.
  33. Chiu,Hsien Kuang; Perng,Baw Ching; Tao,Hun Jan. Process for patterning high-k dielectric material. USP2006057037849.
  34. Wilk, Glen David; Ye, Peide. Process for semiconductor device fabrication in which a insulating layer is formed on a semiconductor substrate. USP2004086770536.
  35. Yao, Liang-Gi; Wang, Ming-Fang; Chen, Shih-Chang; Liang, Mong-Song. Process to make high-K transistor dielectrics. USP2014078785272.
  36. Yao, Liang-Gi; Wang, Ming-Fang; Chen, Shih-Chang; Liang, Mong-Song. Process to make high-K transistor dielectrics. USP2011098012824.
  37. Yao,Liang Gi; Wang,Ming Fang; Chen,Shih Chang; Liang,Mon Song. Process to make high-k transistor dielectrics. USP2006087087480.
  38. Fischer,Bj철rn; Goldbach,Matthias; Jakschik,Stefan; Schl철sser,Till. Semiconductor device and corresponding fabrication method. USP2006057045855.
  39. Ramkumar, Krishnaswamy. Semiconductor topography including a thin oxide-nitride stack and method for making the same. USP2011017867918.
  40. Ramkumar,Krishnaswamy. Semiconductor topography including a thin oxide-nitride stack and method for making the same. USP2008047365403.
  41. Hattangady, Sunil V.; Mavoori, Jaideep; Hu, Che-Jen; Khamankar, Rajesh B.. Semiconductor with a nitrided silicon gate oxide and method. USP2004046716695.
  42. Hattangady, Sunil V.; Mavoori, Jaideep; Hu, Che-Jen; Khamankar, Rajesh B.. Semiconductor with a nitrided silicon gate oxide and method. USP2005106956267.
  43. Liu, Kaiping. Transistors, integrated circuits, systems, and processes of manufacture with improved work function modulation. USP2009117611943.

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