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Flip chip adaptor package for bare die 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/40
  • H01L-023/28
출원번호 US-0911160 (2001-07-23)
발명자 / 주소
  • Moden, Walter L.
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    TraskBritt
인용정보 피인용 횟수 : 49  인용 특허 : 33

초록 ▼

A board for connecting a bare semiconductor die with a bond pad arrangement which does not conform to a master printed circuit board with a specific or standardized pin out, connector pad, or lead placement arrangement. The board comprises a printed circuit board including first elements, such as mi

대표청구항 ▼

A board for connecting a bare semiconductor die with a bond pad arrangement which does not conform to a master printed circuit board with a specific or standardized pin out, connector pad, or lead placement arrangement. The board comprises a printed circuit board including first elements, such as mi

이 특허에 인용된 특허 (33)

  1. Yoneda Yoshihiro (Kawasaki JPX) Ozawa Takashi (Kawasaki JPX), BGA semiconductor device including a plurality of semiconductor chips located on upper and lower surfaces of a first sub.
    상세보기
  2. Mahulikar Deepak ; Hoffman Paul R. ; Braden Jeffrey S., Ball grid array electronic package.
    상세보기
  3. Ikemizu Morihiko,JPX ; Oie Nobuaki,JPX ; Iwasaki Ken,JPX, Electronic device and semiconductor package.
    상세보기
  4. Degani Yinon (Highland Park NJ) Dudderar Thomas D. (Chatham NJ) Han Byung J. (Scotch Plains NJ) Raju Venkataram R. (New Providence NJ), Electronic device package having electronic device boonded, at a localized region thereof, to circuit board.
    상세보기
  5. Eng Kian Teng,SGX ; Chan Min Yu,SGX ; Goh Jing Sua,SGX ; Low Siu Waf,SGX, Flexible pin location integrated circuit package.
    상세보기
  6. Moden Walter L., Flip chip adaptor package for bare die.
    상세보기
  7. Ackermann Karl-Peter (Niederrohrdorf CHX) Berner Gianni (Baden CHX), Highly integrated circuit and method for the production thereof.
    상세보기
  8. Eide Floyd K. (Huntington Beach CA), IC chip package having chip attached to and wire bonded within an overlying substrate.
    상세보기
  9. Shen Ming-Tung (No. 60 ; Lane 328 ; Li-Shan St. Nei-Hu Dist. ; Taipei City TWX), Integrated circuit chip including superimposed upper and lower printed circuit boards.
    상세보기
  10. Lim Thiam B. (Singapore SGX) Saitoh Tadashi (Singapore SGX) Seow Boon Q. (Singapore SGX), Integrated circuit device and method to prevent cracking during surface mount.
    상세보기
  11. Lin Paul T. (Austin TX), Leaded semiconductor device having accessible power supply pad terminals.
    상세보기
  12. Jones Tim (Chandler AZ) Ommen Denise (Phoenix AZ) Baird John (Scottsdale AZ), Low-profile ball-grid array semiconductor package.
    상세보기
  13. Farnworth Warren M. (Nampa ID) Shrock Ed A. (Boise ID) Clifford Scott (Boise ID) King Jerrold L. (Boise ID) Moden Walter (Boise ID), Method for attaching a semiconductor die to a leadframe using a patterned adhesive layer.
    상세보기
  14. Jiang Tongbi ; Schrock Edward, Method for fabricating BGA package using substrate with patterned solder mask open in die attach area.
    상세보기
  15. Conru H. Ward (Essex Junction VT) Irish Gary H. (Jericho VT) Pakulski Francis J. (Shelburne VT) Slattery William J. (Essex Junction VT) Starr Stephen G. (Essex Junction VT) Ward William C. (Burlingto, Method of making a planarized thin film covered wire bonded semiconductor package.
    상세보기
  16. Akram Salman (Boise ID) Wood Alan G. (Boise ID) Farnworth Warren M. (Nampa ID), Method of producing a single piece package for semiconductor die.
    상세보기
  17. Chia Chok J. ; Variot Patrick, Method of providing electrical connection between an integrated circuit die and a printed circuit board.
    상세보기
  18. Currie Thomas P. (St. Paul MN) Goldberg Norman (Dresher PA), Multichip thin film module.
    상세보기
  19. Lin Paul T. (Austin TX) McShane Michael B. (Austin TX), Overmolded semiconductor device having solder ball and edge lead connective structure.
    상세보기
  20. Ma Abraham C. (Milpitas CA) Hsueh Paul Y. J. (Concord CA), Packaged integrated circuit add-on card.
    상세보기
  21. Okinaga Takayuki (Akishima JPX) Otsuka Kanji (Higashiyamato JPX) Akasaki Hiroshi (Ohme JPX), Pin-grid array semiconductor device.
    상세보기
  22. Oh Sang E. (Seongnam KRX), Printed circuit board having solder ball mounting groove pads and a ball grid array package using such a board.
    상세보기
  23. Matsuura Hidekazu,JPX ; Iwazaki Yoshihide,JPX ; Ohta Naoto,JPX, Process for fabricating a crack resistant resin encapsulated semiconductor chip package.
    상세보기
  24. Kohno Ryuji (Ibaraki JPX) Kitano Makoto (Tsuchiura JPX) Nishimura Asao (Ushiku JPX) Yaguchi Akihiro (Ibaraki JPX) Kawai Sueo (Ibaraki JPX), Semiconductor device.
    상세보기
  25. Tsubosaki Kunihiro,JPX ; Tanimoto Michio,JPX ; Nishi Kunihiko,JPX ; Ichitani Masahiro,JPX ; Koike Shunji,JPX ; Suzuki Kazunari,JPX ; Kimoto Ryosuke,JPX ; Anjoh Ichiro,JPX ; Jin Taisei,JPX ; Iwaya Aki, Semiconductor device.
    상세보기
  26. Sato Mitsutaka (Kawasaki JPX) Kasai Junichi (Kawasaki JPX) Yoshimoto Masanori (Kawasaki JPX) Takeshita Kouichi (Satsuma JPX), Semiconductor device affixed to an upper and a lower leadframe.
    상세보기
  27. Thompson Kenneth R. (Sunrise FL) Banerj Kingshuk (Plantation FL) da Costa Alves Francisco (Boca Raton FL), Semiconductor device with controlled spread polymeric underfill.
    상세보기
  28. Akram Salman ; Wood Alan G. ; Farnworth Warren M., Stackable chip scale semiconductor package with mating contacts on opposed surfaces.
    상세보기
  29. Toh Tuck Fook,SGX ; Leong Chew Weng,SGX ; Yew Chee Kiang,SGX ; Ong Pang Hup,SGX, Thin chip-size integrated circuit package.
    상세보기
  30. Kryzaniwsky Bohdan R. (Hopewell Junction NY), Three-dimensional memory card structure with internal direct chip attachment.
    상세보기
  31. Lin Paul T. (Austin TX), Three-dimensional multi-chip pad array carrier.
    상세보기
  32. Lee Kyu Jin,KRX ; Jeong Do Soo,KRX ; Kim Jae June,KRX, Wire bond packages for semiconductor chips and related methods and assemblies.
    상세보기
  33. Higgins ; III Leo M. (Austin TX), Z-axis compliant mechanical IC wiring substrate and method for making the same.
    상세보기

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  1. Lee, Sang Ho; Ju, Jong Wook; Kwon, Hyeog Chan, Adhesive/spacer island structure for multiple die package.
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  2. Lee, Sang Ho; Ju, Jong Wook; Kwon, Hyeog Chan; Karnezos, Marcos, Adhesive/spacer island structure for stacking over wire bonded die.
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  3. Lee, Teck Kheng; Lee, Kian Chai, Apparatus for package reduction in stacked chip and board assemblies.
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  4. Shim, Il Kwon; Han, Byung Joon; Ramakrishna, Kambhampati; Chow, Seng Guan, Encapsulant cavity integrated circuit package system and method of fabrication thereof.
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  5. Moden, Walter L., Grid array packages.
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  6. Moden, Walter L., Grid array packages and assemblies including the same.
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  7. Moden,Walter, Imaging system.
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  9. Pendse, Rajendra D., Integrated circuit package system including zero fillet resin.
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  10. Shim, Il Kwon; Han, Byung Joon; Ramakrishna, Kambhampati; Chow, Seng Guan, Integrated circuit package system with an encapsulant cavity and method of fabrication thereof.
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  11. Chow, Seng Guan; Shim, II Kwon; Han, Byung Joon, Integrated circuit package system with exposed interconnects.
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  12. Shim, Il Kwon; Han, Byung Joon; Ramakrishna, Kambhampati; Chow, Seng Guan, Integrated circuit packaging system with a component in an encapsulant cavity and method of fabrication thereof.
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  13. Moden, Walter, Method for fabricating image sensor semiconductor package.
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  14. Karnezos,Marcos; Carson,Flynn, Method for making a semiconductor multi-package module having inverted bump chip carrier second package.
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  15. Karnezos,Marcos, Method for making semiconductor multi-package module having inverted second package and including additional die or package stacked on second package.
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  16. Karnezos, Marcos; Carson, Flynn; Kim, Youngcheol, Method for making semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package.
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  17. Lee,Teck Kheng; Lee,Kian Chai, Method for package reduction in stacked chip and board assemblies.
    상세보기
  18. Karnezos,Marcos, Method of fabricating a semiconductor assembly including chip scale package and second substrate with exposed substrate surfaces on upper and lower sides.
    상세보기
  19. Karnezos, Marcos, Method of fabricating a semiconductor multi package module having an inverted package stacked over ball grid array (BGA) package.
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  20. Karnezos,Marcos, Method of fabricating a semiconductor multi-package module having a second package substrate with an exposed metal layer wire bonded to a first package substrate.
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  21. Karnezos,Marcos, Method of fabricating a semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package.
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  22. Karnezos,Marcos, Method of fabricating a semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package.
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  23. Karnezos,Marcos, Method of fabricating a semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA).
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  24. Karnezos, Marcos, Method of fabricating a semiconductor multipackage module including a processor and memory package assemblies.
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  25. Karnezos,Marcos, Method of fabricating a semiconductor stacked multi-package module having inverted second package.
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  26. Karnezos, Marcos, Method of fabricating module having stacked chip scale semiconductor packages.
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  27. Karnezos,Marcos, Module having stacked chip scale semiconductor packages.
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  28. Chow, Seng Guan; Kuan, Heap Hoe, Multi-chip package system.
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  29. Karnezos, Marcos, Multiple chip package module having inverted package stacked over die.
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  30. Karnezos, Marcos, Multiple chip package module including die stacked over encapsulated package.
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  31. Cobbley, Chad, Process for providing electrical connection between a semiconductor die and a semiconductor die receiving member.
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  32. Karnezos,Marcos; Shim,IL Kwon; Han,Byung Joon; Ramakrishna,Kambhampati; Chow,Seng Guan, Semiconductor assembly including chip scale package and second substrate with exposed surfaces on upper and lower sides.
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  33. Karnezos,Marcos; Carson,Flynn, Semiconductor multi-package module having inverted bump chip carrier second package.
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  34. Karnezos,Marcos, Semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package.
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  35. Karnezos,Marcos, Semiconductor multi-package module having inverted second package and including additional die or stacked package on second package.
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  36. Karnezos, Marcos, Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package.
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  37. Karnezos,Marcos, Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package.
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  38. Karnezos,Marcos, Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package.
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  39. Karnezos, Marcos; Carson, Flynn; Kim, Youngcheol, Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package.
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  40. Karnezos,Marcos; Carson,Flynn; Kim,Youngcheol, Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package.
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  41. Karnezos,Marcos; Carson,Flynn, Semiconductor package including second substrate and having exposed substrate surfaces on upper and lower sides.
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  42. Karnezos,Marcos, Semiconductor stacked multi-package module having inverted second package.
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  43. Karnezos, Marcos, Semiconductor stacked multi-package module having inverted second package and electrically shielded first package.
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  44. Karnezos,Marcos; Shim,Il Kwon; Han,Byung Joon; Ramakrishna,Kambhampati; Chow,Seng Guan, Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides.
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  45. Moden, Walter L., Stackable semiconductor device assemblies.
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  46. Cobbley, Chad A.; Jackson, Timothy L., Stacked die module including multiple adhesives that cure at different temperatures.
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  47. Carson, Flynn, Stacked integrated circuit package system and method of manufacture therefor.
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  48. Kwon, Hyeog Chan; Karnezos, Marcos, Stacked semiconductor package having adhesive/spacer structure and insulation.
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  49. Huang, Chien Ping; Huang, Chih-Ming; Chuang, Jui-Yu; Chan, Lien-Chi, Window-type ball grid array semiconductor package with lead frame as chip carrier and method for fabricating the same.
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