A superconducting cable (1) for high power with at least one phase comprises a superconducting core (2) wherein a plurality of elements (3) are housed, which are structurally independent and magnetically uncoupled, each of which includes--for each phase--a couple of phase and neutral coaxial conduct
A superconducting cable (1) for high power with at least one phase comprises a superconducting core (2) wherein a plurality of elements (3) are housed, which are structurally independent and magnetically uncoupled, each of which includes--for each phase--a couple of phase and neutral coaxial conductors, each formed by at least a layer of superconducting material, electrically insulated from one another by interposition of a dielectric material (8). Thanks to the distribution of the superconducting material into several coaxial conductive elements (3), the cable (1) allows to transmit high current amounts in conditions of superconductivity, while using a high-temperature superconducting material sensitive to the magnetic field.
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A superconducting cable (1) for high power with at least one phase comprises a superconducting core (2) wherein a plurality of elements (3) are housed, which are structurally independent and magnetically uncoupled, each of which includes--for each phase--a couple of phase and neutral coaxial conduct
A superconducting cable (1) for high power with at least one phase comprises a superconducting core (2) wherein a plurality of elements (3) are housed, which are structurally independent and magnetically uncoupled, each of which includes--for each phase--a couple of phase and neutral coaxial conductors, each formed by at least a layer of superconducting material, electrically insulated from one another by interposition of a dielectric material (8). Thanks to the distribution of the superconducting material into several coaxial conductive elements (3), the cable (1) allows to transmit high current amounts in conditions of superconductivity, while using a high-temperature superconducting material sensitive to the magnetic field. omprising: a carrier substrate including a plurality of conductive traces disposed thereon; a packaging substrate including a first surface having a recess disposed therein and a plurality of conductive leads formed thereon, each conductive lead having an inner end proximate the recess and an outer end coupled with a corresponding one of the conductive traces; a first die attached to the packaging substrate within the recess and having a plurality of first bond pads disposed thereon, each first bond pad being electrically coupled to one of the inner ends; and a second die attached to the first die and having a plurality of second bond pads disposed thereon, each second bond pad being electrically coupled to one of the inner ends, the first surface of the packaging substrate being proximate the carrier substrate, wherein at least some of the inner ends comprise first contact pads disposed within the recess, each of the first bond pads directly contacting one of the first contact pads. 7. The multi-chip module of claim 6 wherein the outer ends of the conductive leads comprise solder bumps engageable with terminals on the carrier substrate. 8. The multi-chip module of claim 6 wherein the packaging substrate comprises an electrically conductive substrate, further comprising an electrically insulative layer formed between the conductive leads and the packaging substrate. 9. A circuit board, comprising: a carrier substrate including a plurality of electrically conductive circuits disposed thereon; a stacked die package including: a packaging substrate including a first surface having a recess disposed therein and a plurality of conductive leads coupled thereto, each conductive lead having an inner end proximate the recess and an outer end coupled with a corresponding one of the circuits on the carrier substrate; a first die attached to the packaging substrate within the recess and having a plurality of first bond pads disposed thereon, each first bond pad being electrically coupled to one of the inner ends; and a second die attached to the first die and having a plurality of second bond pads disposed thereon, each second bond pad being electrically coupled to one of the inner ends, the first surface of the packaging substrate being proximate the carrier substrate whereby the packaging substrate at least partially encloses and protects both the first and second die, wherein at least some of the inner ends comprise first contact pads disposed within the recess, each of the first bond pads directly contacting one of the first contact pads. 10. The multi-chip module of claim 9 wherein at least some of the outer ends of the conductive leads comprise solder bumps coupled to the corresponding circuits on the carrier substrate. 11. The multi-chip module of claim 9 wherein the packaging substrate comprises an electrically conductive substrate, further comprising an electrically insulative layer formed between the conductive leads and the packaging substrate. 12. The multi-chip module of claim 9 wherein the first die is a flip chip mounted die and the second bond pads are wire-bonded to the inner ends of the conductive leads. 13. A multi-chip module, comprising: a carrier substrate including a plurality of electrically conductive circuits disposed thereon; a packaging substrate including a first surface having a recess disposed therein and a plurality of conductive leads coupled thereto, each conductive lead having an inner end proximate the recess and an outer end coupled with a corresponding one of the circuits on the carrier substrate; a first die attached to the packaging substrate within the recess and having a plurality of first bond pads disposed thereon, each first bond pad being electrically coupled to one of the inner ends; and a second die attached to the first die and having a plurality of second bond pads disposed thereon, each second bond pad being electrically coupled to one of the inner ends, the first
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이 특허에 인용된 특허 (11)
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