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A capacitor array device is described including a multiple capacitor chip for mounting upon an electronic circuit board. The device includes a device body defined by a plurality of dielectric layers and conductive layers arranged in a stack to form a number of adjacent capacitors. Barium titanate ma

A capacitor array device is described including a multiple capacitor chip for mounting upon an electronic circuit board. The device includes a device body defined by a plurality of dielectric layers and conductive layers arranged in a stack to form a number of adjacent capacitors. Barium titanate may be employed as a dielectric. The capacitor array device includes a plurality of terminal structures electrically connected to the electrode plates. The device typically includes a sintered body of a multilayer ceramic material in which multiple electrode layers are stacked with dielectric layers being located between the electrode layers. Multiple combinations of capacitance values may be used within the array. An array having two, three, four, five, six, or more capacitors may be constructed, such that certain of the capacitors have about the same capacitance value, while other capacitors within the array have other different capacitance values. The capacitance values among the adjacent capacitors within the array may differ by ratios as high as 1:100 or more.

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A capacitor array device is described including a multiple capacitor chip for mounting upon an electronic circuit board. The device includes a device body defined by a plurality of dielectric layers and conductive layers arranged in a stack to form a number of adjacent capacitors. Barium titanate ma

A capacitor array device is described including a multiple capacitor chip for mounting upon an electronic circuit board. The device includes a device body defined by a plurality of dielectric layers and conductive layers arranged in a stack to form a number of adjacent capacitors. Barium titanate may be employed as a dielectric. The capacitor array device includes a plurality of terminal structures electrically connected to the electrode plates. The device typically includes a sintered body of a multilayer ceramic material in which multiple electrode layers are stacked with dielectric layers being located between the electrode layers. Multiple combinations of capacitance values may be used within the array. An array having two, three, four, five, six, or more capacitors may be constructed, such that certain of the capacitors have about the same capacitance value, while other capacitors within the array have other different capacitance values. The capacitance values among the adjacent capacitors within the array may differ by ratios as high as 1:100 or more. rein the reference plane is obtained through calculation performed by the calculating section such that a maximum degree of the unevenness of the surface of the semiconductor wafer within the effective element region of the predetermined region is minimized. 3. The pattern-exposure apparatus according to claim 1, wherein said unevenness measuring section has a light source for applying light and a sensor for receiving light and outputting an electrical signal, and said unevenness measuring section measures a distance from the wafer by applying light to the semiconductor wafer from the light source and receiving light reflected from a surface of the semiconductor wafer by the sensor and outputs the unevenness data. 4. The pattern-exposure apparatus according to claim 1, wherein said light-exposure section has a light source for applying light and a mask having a circuit pattern drawn thereon, and said light exposure section transfers the circuit pattern drawn on the mask onto the semiconductor wafer by use of light applied from the light source. 5. The pattern-exposure apparatus according to claim 1, further comprising a stage for mounting the semiconductor wafer thereon, wherein the inclination control mechanism controls inclination of the semiconductor wafer by controlling inclination of the stage. 6. The pattern-exposure apparatus according to claim 4, further comprising a mask scan mechanism for scanning the mask, a stage for mounting the semiconductor wafer thereon, and a stage scan mechanism for scanning the stage, wherein the circuit pattern on the mask is transferred onto the semiconductor wafer by synchronously scanning the mask and the stage by the mask scan mechanism and the stage scan mechanism, respectively. 7. A pattern-exposure apparatus for a semiconductor wafer comprising: a light-exposure section applying light to a predetermined region on a semiconductor wafer having an effective chip region and an ineffective chip region, said effective chip region being set within an effective element region, in which an element is formed, and required for forming a single chip therein, said ineffective chip region including an ineffective element region, in which no element is formed and required for forming a single chip therein, and said predetermined region including at least either one of or a part of both the effective chip region and the ineffective chip region; a determination section determining that each of a plurality of sites within the predetermined region is either the effective element region or the ineffective element region; an unevenness measuring section measuring unevenness of sites only having the effective chip region, which are selected from said plurality of sites within the predetermined region by eliminating sites having the ineffective chip region determined by said determination section and outputting unevenness data; a calculating section obtaining a reference plane through calculation using unevenness data output from the unevenness measuring section, said reference plane being used as a reference when light is applied to the predetermined region by said light exposures section; and an inclination control mechanism controlling inclination of the semiconductor wafer in accordance with the reference plane obtained through the calculation performed by the calculating section. 8. The pattern-exposure apparatus according to claim 7, wherein the reference plane is obtained through calculation performed by the calculating section such that a maximum degree of the unevenness of the surface of the semiconductor wafer within the effective element region of the predetermined region is minimized. 9. The pattern-exposure apparatus according to claim 7, wherein said unevenness measuring section has a light source for applying light and a sensor for receiving light and outputting an electrical signal, and said unevenness measuring section measures a distance from the wafer by applying light to the se miconductor wafer from the light source and receiving light reflected from a surface of the semiconductor wafer by the sensor and outputs the unevenness data. 10. The pattern-exposure apparatus according to claim 7, wherein said light-exposure section has a light source for applying light and a mask having a circuit pattern drawn thereon, and said light exposure section transfers the circuit pattern drawn on the mask onto the semiconductor wafer by use of light applied from the light source. 11. The pattern-exposure apparatus according to claim 7, further comprising a stage for mounting the semiconductor wafer thereon, wherein the inclination control mechanism controls inclination of the semiconductor wafer by controlling inclination of the stage. 12. The pattern-exposure apparatus according to claim 10, further comprising a mask scan mechanism for scanning the mask, a stage for mounting the semiconductor wafer thereon, and a stage scan mechanism for scanning the stage, wherein the circuit pattern on the mask is transferred onto the semiconductor wafer by synchronously scanning the mask and the stage by the mask scan mechanism and the stage scan mechanism, respectively. 13. A pattern exposure method for a semiconductor wafer comprising the steps of: determining whether or not at least a part of an ineffective chip region is included in a predetermined region on the semiconductor wafer; said ineffective chip region including an ineffective element region in which no element is formed and required for forming a single chip; measuring unevenness of a surface of the semiconductor wafer at a plurality of sites of the predetermined region excluding the ineffective chip region and outputting unevenness data; obtaining a reference plane for use in applying light to the predetermined region, through calculation using the unevenness data output; and controlling inclination of the semiconductor wafer in accordance with the reference plane obtained. 14. The pattern-exposure method according to claim 13, wherein the reference plane is obtained through calculation performed such that a maximum degree of the unevenness of the surface of the semiconductor wafer within the effective chip region of the predetermined region is minimized. 15. The pattern-exposure method according to claim 13, wherein the unevenness data is obtained by measuring a distance from the wafer to a light source by applying light to the semiconductor wafer from the light source and receiving light reflected from a surface of the semiconductor wafer by a sensor. 16. The pattern-exposure method according to claim 13, wherein further comprising a step of applying light to the predetermined region so as to match a light-exposure focusing surface with the reference plane after the step of controlling inclination of the semiconductor wafer. e LCD panel is a lower substrate, and the other substrate is an upper substrate, wherein one substrate of the pixel array transparent substrate and the opposing transparent substrate of the right side LCD panel is an upper substrate, and the other substrate is a lower substrate, and wherein a right edge of the left side LCD panel is bonded to a left edge of the right side LCD panel, to bond the one substrate of the left side LCD panel and the other substrate of the right side LCD panel and to bond the other substrate of the left side LCD panel and the one substrate of the right side LCD panel.