IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0375657
(1999-08-17)
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발명자
/ 주소 |
- Alur, Rajeev
- Yannakakis, Mihalis
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출원인 / 주소 |
|
대리인 / 주소 |
Hitt Gaines & Boisbrun P.C.
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인용정보 |
피인용 횟수 :
6 인용 특허 :
5 |
초록
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Model checking for message sequence charts (MSCs), message sequence chart graphs and hierarchical message sequence chart graphs (HMSCs) is provided. To verify the behavior of a given MSC, MSC graph and HMSC, a specification automaton is constructed. This specification automaton specifies the undesir
Model checking for message sequence charts (MSCs), message sequence chart graphs and hierarchical message sequence chart graphs (HMSCs) is provided. To verify the behavior of a given MSC, MSC graph and HMSC, a specification automaton is constructed. This specification automaton specifies the undesirable executions of the model under analysis. From the model under analysis, linearizations are defined from the model and a finite test automaton is constructed from the linearizations. The test automaton and the specification automaton are combined and it is determined whether there is an execution in the intersection. Where no state in the specification automaton is reachable from the test automaton, the model is verified.
대표청구항
▼
Model checking for message sequence charts (MSCs), message sequence chart graphs and hierarchical message sequence chart graphs (HMSCs) is provided. To verify the behavior of a given MSC, MSC graph and HMSC, a specification automaton is constructed. This specification automaton specifies the undesir
Model checking for message sequence charts (MSCs), message sequence chart graphs and hierarchical message sequence chart graphs (HMSCs) is provided. To verify the behavior of a given MSC, MSC graph and HMSC, a specification automaton is constructed. This specification automaton specifies the undesirable executions of the model under analysis. From the model under analysis, linearizations are defined from the model and a finite test automaton is constructed from the linearizations. The test automaton and the specification automaton are combined and it is determined whether there is an execution in the intersection. Where no state in the specification automaton is reachable from the test automaton, the model is verified. r. 11. A method for providing a discriminator device, comprising the steps of: (A) controlling an output with a first one or more threshold devices; (B) receiving said output with a second one or more threshold devices; and (C) generating a feedback to said first one or more threshold devices, wherein (i) said feedback is configured to force a reset condition if a metastable event occurs and (ii) said first one or more threshold devices comprise inverters with high thresholds, and (iii) said second one or more threshold devices comprise inverters with low thresholds. 12. The method according to claim 11, wherein steps (A) and (B) are further responsive to an input signal. 13. The method according to claim 12, wherein step (C) further comprises: switching one or more devices to control said output. 14. The method according to claim 13, wherein said one or more devices comprises MOS transistors. 15. The method according to claim 13, wherein step (C) is further responsive to a reset signal. 16. The method according to claim 15, wherein step (C) further comprises: resetting said first one or more threshold devices. 17. An apparatus comprising: a first one or more threshold devices comprising inverters with a first threshold configured to control an output; a second one or more threshold devices (i) comprising inverters with a second threshold lower than said first threshold and (ii) configured to receive said output; and a logic device (i) coupled to said second one or more threshold devices and (ii) configured to provide a feedback to said first one or more threshold devices, wherein said feedback is configured to force a reset condition if a metastable event occurs. ical-Grained Si", J. Appl. Phys., 71, 3538-3543, (Apr. 1992). Watanabe, H., et al., "Hemispherical Grained Silicon (HSG-Si) Formation on In-Situ Phosphorous Doped Amorphous-Si Using the Seeding Method", Extended Abstracts of the 1992 International Conference on Solid State Devices and Materials, Tsukuba, Japan, 422-424, (1992). Watanabe, S., et al., "A Novel Circuit Technology with Surrounding Gate Transistors (SGT's) for Ultra High Density DRAM's", IEEE Journal of Solid-State Circuits, 30, 960-971, (Sep. 1995). Wooley, et al., "Experimental Results and Modeling Techniques for Substrate Noise in Mixed Signal Integrated Circuits", IEEE Journal of Solid State Circuits, vol. SC-28, 420-30, (1993). Yamada, T., et al., "A New Cell Structure with a Spread Source/Drain (SSD) MOSFET and a Cylindrical Capacitor for 64-Mb DRAM's", IEEE Transactions on Electron Devices, 38, 2482-2486, (Nov. 1991). Yamada, T., et al., "Spread Source/Drain (SSD) MOSFET Using Selective Silicon Growth for 64Mbit DRAMs", 1989 IEEE International Electron Devices Meeting, Technical Digest, Washington, D.C., 35-38, Dec. 3-6, 1989). Yoshikawa, K., "Impact of Cell Threshold Voltage Distribution in the Array of Flash Memories on Scaled and Multilevel Flash Cell Design", 1996 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI, 240-241, (Jun. 11-13, 1996). Rhyne, Fundamentals of Digital Systems design, 1973, Prentice, pp. 70-71.
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