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System and method for controlling access to a privilege-partitioned address space with a fixed set of attributes

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-012/14
  • G06F-013/00
출원번호 US-0626615 (2000-07-27)
발명자 / 주소
  • Christie, David S.
출원인 / 주소
  • Advanced Micro Devices, Inc.
대리인 / 주소
    Merkel, Lawrence J.
인용정보 피인용 횟수 : 8  인용 특허 : 33

초록

A system and method for controlling access to privilege partitioned address space for a model specific register file. A superscalar microprocessor includes a plurality of model specific registers (MSRs). MSRs differ between various implementations of a microprocessor architecture. The MSRs are alloc

대표청구항

A system and method for controlling access to privilege partitioned address space for a model specific register file. A superscalar microprocessor includes a plurality of model specific registers (MSRs). MSRs differ between various implementations of a microprocessor architecture. The MSRs are alloc

이 특허에 인용된 특허 (33)

  1. Brant William Alexander ; Tang Edde Tin-Shek, Address protection circuit and method for preventing access to unauthorized address rangers.
  2. Wolf Gerhard (Munich DT), Associative memory having separately associable zones.
  3. Revilla Juan G. (Austin TX) Parmet Art (Burlington MA), Data processing system and method for providing memory access protection using transparent translation registers and def.
  4. Le Chinh H. (Austin TX) Eifert James B. (Austin TX), Data processor with a multi-level protection mechanism, multi-level protection circuit, and method therefor.
  5. Pflum Marty L., Dependency checking structure for a pair of caches which are accessed from different pipeline stages of an instruction.
  6. Shigeeda Akio, Electronic system with circuitry for selectively enabling access to configuration registers used by a memory controller.
  7. Gaither Blaine D. (Sierra Madre CA) Farley ; IV William W. (Pasadena CA) Johnson Albert (Altadena CA) Parker Brian L. (Pasadena CA), Extended address generating apparatus and method.
  8. Dao Tich T. (Cupertino CA) Burke Gary R. (Cupertino CA), Floating point microprocessor with directable two level microinstructions.
  9. Torng Hwa C. (Ithaca NY), Instruction issuing mechanism for processors with multiple functional units.
  10. Pickett James K. ; Christie David S., Instruction redefinition using model specific registers.
  11. Favor John G. (San Jose CA) Van Dyke Korbin (Fremont CA) Stiles David R. (Sunnyvale CA), Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency.
  12. Christie David S., Method and mechanism for checking integrity of byte enable signals.
  13. Tran Thang M. ; Pflum Marty L. ; Witt David B. ; Johnson William M., Method for transferring data between a pair of caches configured to be accessed from different stages of an instruction.
  14. Schmidt Karl-Heinz (Aying DEX) Menache Georg (Mnchen DEX) Waidelich Wilhelm (Mnchen DEX), Method of protecting programs and data in a computer against unauthorized access and modification by monitoring address.
  15. Dutton Drew J. ; Christie David S., Microprocessor and method of using a segment override prefix instruction field to expand the register file.
  16. Tran Thang M. ; Witt David B. ; Johnson William M., Microprocessor configured to swap operands in order to minimize dependency checking logic.
  17. Dutton Drew J. ; Christie David S., Microprocessor using an instruction field to expand the condition flags and a computer system employing the microprocess.
  18. Dutton Drew J. ; Christie David S., Microprocessor using an instruction field to specify condition flags for use with branch instructions and a computer sys.
  19. Dutton Drew J. (Austin TX) Christie David S. (Austin TX), Microprocessor using an instruction field to specify expanded functionality and a computer system employing same.
  20. Christie David S., Microprocessor with built-in instruction tracing capability.
  21. Witt David B., Microprocessor with dynamically extendable pipeline stages and a classifying circuit.
  22. Johnson William M. (San Jose CA), Multiple instruction decoder for minimizing register port requirements.
  23. Gupta Smeeta (Saratoga CA) Perlman Robert M. (San Jose CA) Lynch Thomas W. (Austin TX) McMinn Brian D. (Austin TX), Normalizing pipelined floating point processing unit.
  24. Kuriyama Kazunori (Kokubunji JPX) Shintani Yooichi (Kokubunji JPX) Yamaoka Akira (Hachioji JPX) Shonai Tohru (Kokubunji JPX) Kamada Eiki (Hachioji JPX) Inoue Kiyoshi (Tokyo JPX), Pipelined data processor capable of decoding and executing plural instructions in parallel.
  25. Perlman Robert M. (San Jose CA) Sobel Prem (Sunnyvale CA) McMinn Brian D. (Austin TX) Thaden Robert C. (Austin TX) Tamura Glenn A. (Austin TX) Lynch Thomas W. (Austin TX) Vesgesna Raju (Austin TX), Pipelined floating point processing unit.
  26. McFarland Harold L. (San Jose CA) Stiles David R. (Sunnyvale CA) Van Dyke Korbin S. (Fremont CA) Mehta Shrenik (San Jose CA) Favor John G. (San Jose CA) Greenley Dale R. (San Jose CA) Cargnoni Robert, Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tag.
  27. Tran Thang M., Recorder buffer capable of detecting dependencies between accesses to a pair of caches.
  28. Christie David S., Segmentation suspend mode for real-time interrupt support.
  29. Pflum Marty L., Superscalar microprocessor including a cache configured to detect dependencies between accesses to the cache and anothe.
  30. Tran Thang M. ; Witt David B. ; Johnson William M., Superscalar microprocessor including a reorder buffer which detects dependencies between accesses to a pair of caches.
  31. Christie David S., System and method of controlling access to privilege partitioned address space for a model specific register file.
  32. Gillespie Byron R. (Phoenix AZ) Garbus Elliot D. (Scotsdale AZ) Kahn Mitchell A. (San Jose CA) Johnson Thomas M. (Tempe AZ) O\Connor Dennis M. (Chandler AZ) Heeb Jay S. (Gilbert AZ), System for protecting memory accesses by comparing the upper and lower bounds addresses and attribute bits identifying u.
  33. Johnson William M. (San Jose CA), System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information sto.

이 특허를 인용한 특허 (8)

  1. Brennan, Todd, Centralized timed analysis in a network security system.
  2. Brennan, Todd, Content extractor and analysis system.
  3. Strongin, Geoffrey S.; Barnes, Brian C.; Schmidt, Rodney W., Memory management system and method providing increased memory access security.
  4. Strongin, Geoffrey S.; Barnes, Brian C.; Schmidt, Rodney, Method and apparatus for improved security in a data processor.
  5. McCarthy, Daniel M.; Circello, Joseph C.; Hausman, Kristen A., Methods and systems for transitioning between a user state and a supervisor state based on a next instruction fetch address.
  6. Strongin,Geoffrey S.; Barnes,Brian C.; Schmidt,Rodney W., System and method for handling device accesses to a memory providing increased memory access security.
  7. McKee, Bret A., System and method for monitoring execution of privileged instructions.
  8. Fischer, Stephen A.; Rodgers, Dion; Sutton, James A., User opt-in processor feature control capability.
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