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Method and apparatus for selectively viewing nets within a database editor tool

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-017/50
출원번호 US-0789027 (1997-01-27)
발명자 / 주소
  • Garnett, Robert E.
  • Kerzman, Joseph P.
  • Rezek, James E.
  • Aubel, Mark D.
출원인 / 주소
  • Unisys Corporation
대리인 / 주소
    Johnson, Charles A.Starr, Mark T.Nawrocki, Rooney & Sivertson P.A.
인용정보 피인용 횟수 : 39  인용 특허 : 36

초록

A method and apparatus for selectively viewing nets within a database editor tool. The present invention provides four primary features for selectively viewing nets. First, the present invention contemplates selecting a number of objects, and viewing only those nets that are either driven from or re

대표청구항

A method and apparatus for selectively viewing nets within a database editor tool. The present invention provides four primary features for selectively viewing nets. First, the present invention contemplates selecting a number of objects, and viewing only those nets that are either driven from or re

이 특허에 인용된 특허 (36)

  1. Kawata Tetsuro (Kanagawa JPX), Apparatus for optimizing hierarchical circuit data base and method for the apparatus.
  2. Baisuck Allen (San Jose CA) Fairbank Richard L. (Schenectady NY) Gowen ; III Walter K. (Troy NY) Henriksen Jon R. (Latham NY) Hoover ; III William W. (Ballston Lake NY) Huckabay Judith A. (Union City, Architecture and method for data reduction in a system for analyzing geometric databases.
  3. Saucier Gabriele (Bresson FRX) Poirot Franck J. (Valbonne FRX), Automatic synthesis of integrated circuits employing controlled input dependency during a decomposition process.
  4. Hooper Donald F. (Northboro MA) Kundu Snehamay (Marlboro MA), Bitwise implementation mechanism for a circuit design synthesis procedure.
  5. Igarashi Shinichi (Tokyo JPX), CAD system for generating a schematic diagram of identifier sets connected by signal bundle names.
  6. Talbott Marvin T. (Plano TX) Hutchison Katherine K. (Dallas TX), Computer tool for system level design.
  7. Kaiser Richard R. (10810 NW. La Cassel Crest La. Portland OR 97229) Bartel Robert W. (Rte. 2 ; P.O. Box 107 Gaston OR 97119), Critical path analyzer with path context window.
  8. Hooper Donald F. (Northboro MA), Data base access mechanism for rules utilized by a synthesis procedure for logic circuit design.
  9. Hernandez Celimo P. (San Jose CA) Coultas Robyn D. (Atherton CA), Expression promotion for hierarchical netlisting.
  10. Kamijima Shinji (Tokyo JPX), Floor-planning apparatus for hierarchical design of LSI.
  11. Seyler Mark R. (Portland OR), Graph-based programming system and associated method.
  12. Modarres Hossein (Mountain View CA) Raam Susan (Fremont CA) Lai Jiun-Hao (Santa Clara CA), Hierarchical floorplanner.
  13. Mastellone Mitchel A. (New Brunswick NJ), Hierarchical net list derivation system.
  14. Do Cuong (San Jose CA) Wei Ruey-Sing (Fremont CA), Hierarchical ordering of logical elements in the canonical mapping of net lists.
  15. Rubin Steven M. (Portola Valley CA), Integrated electric design system with automatic constraint satisfaction.
  16. Talbott Marvin T. (Plano TX) Burks Henry L. (Dallas TX) Shaw Richard W. (Plano TX) Amundsen Michael (Dallas TX) Hutchison Katherine K. (Dallas TX) Strasburg Donald D. (Plano TX), Method and apparatus for aiding system design.
  17. Kionka Daniel P. (San Jose CA), Method and apparatus for optimizing computer file compilation.
  18. Sharma Balmukund K. (Santa Clara CA) Mahmood Mossaddeq (San Jose CA), Method and apparatus for synthesizing datapaths for integrated circuit design and fabrication.
  19. Talbott Marvin T. (Plano TX) Burks Henry L. (Dallas TX) Shaw Richard W. (Plano TX) Strasburg Donald D. (Plano TX) Hutchison Katherine K. (Dallas TX), Method and apparatus for system design.
  20. Dangelo Carlos (Los Gatos CA) Watkins Daniel (Los Altos CA) Mintz Doron (Sunnyvale CA), Method and system for creating and validating low level description of electronic design from higher level, behavior-ori.
  21. Kim Michelle Y. (Scarsdale NY), Method and system for providing a non-rectangular floor plan.
  22. Matsunaga Yusuke (Yokohama JPX), Method for changing an arrangement of an initial combinational circuit to satisfy prescribed delay time by computing per.
  23. Duncan Robert G. (Castroville CA), Method for entering state flow diagrams using schematic editor programs.
  24. Duncan Robert G. (Castroville CA), Method for entering state flow diagrams using schematic editor programs.
  25. Morita Masato (Hadano JPX) Ikariya Yukio (Hadano JPX) Sakataya Yoshinori (Hadano JPX) Miyoshi Masayuki (Hadano JPX), Method for generating logic circuit data.
  26. Biro Larry L. (210 Bullard Rd. Oakham MA 01068) Pan Jengwei (6 Marylou Cir. Westboro MA 01581), Method for performing integrated section-level and full-chip timing verification for custom microprocessor designs.
  27. Petrus Edwin S. (Santa Clara CA), Method for preparing and dynamically loading context files.
  28. Nishiyama Tamotsu (Hirakata JPX) Ikeda Kazushi (Tsu JPX) Matsunaga Tomoko (Kumamoto JPX), Method of and system for automatically generating network diagrams.
  29. Altheimer Michel (Antibes FRX) Gravoulet Valery F. (Valbonne FRX) Holt Paul M. (Antibes FRX) Riherd Frank T. (Nice FRX), Methods of operating cell libraries and of realizing large scale integrated circuits using a programmed compiler includi.
  30. Minagawa Eiji,JPX ; Uraguchi Hisashi,JPX, Path analyzing displaying apparatus for designing logic circuit.
  31. Sturges Jay J. (Orangevale CA), Process oriented logic simulation having stability checking.
  32. Lee Kaiwin (Sunnyvale CA) Chung Lu (Sunnyvale CA) Lin Chin-Hsen (Milpitas CA) Liao Yuh-Zen (Saratoga CA) Wuu Stephen (Sunnyvale CA), Routing algorithm method for standard-cell and gate-array integrated circuit design.
  33. Hooper Donald F. (Northboro MA) Kundu Snehamay (Marlboro MA), Rule structure in a procedure for synthesis of logic circuits.
  34. Dangelo Carlos (Los Gatos CA) Nagasamy Vijay (Union City CA), Specification and design of complex digital systems.
  35. Brasen Daniel R. (San Francisco CA) Ashtaputre Sunil V. (San Jose CA), Symbolic routing guidance for wire networks in VLSI circuits.
  36. Imahashi Masahiko (Tokyo JPX), System for creating datapath circuit layout.

이 특허를 인용한 특허 (39)

  1. Lin, Shyh-Chang; Lee, Chia-Huei; Lu, Yu-Sheng; Ho, Bang-Hwa, Automatic schematic diagram generation using topology information.
  2. Varadarajan,Ravi, Bus representation for efficient physical synthesis of integrated circuit designs.
  3. Dinter,Matthias; Dirks,Juergen; Klemt,Roland, Cell builder for different layer stacks.
  4. He, Zheng-Yu, Computer aided design system and method.
  5. Wu,Fu Chung; Lee,Chun Liang; Chen,Shu Yun; Huang,Jui Chi; Peng,Tze Hsin; Peng,Kuang Yu, Computer-assisted electronic component schematic linking method.
  6. Wheeler,William R.; Adiletta,Matthew J., Gate estimation process and method.
  7. Wheeler,William R.; Adiletta,Matthew J., Generating a logic design.
  8. Eshima,Takashi, Layout method of semiconductor integrated circuit and cell frame standardization program.
  9. Wheeler,William R.; Fennell,Timothy J.; Adiletta,Matthew J., Logic simulation.
  10. Sahouria, Emile Y.; Zhang, Weidong, Mask creation with hierarchy management using cover cells.
  11. Sahouria, Emile Y.; Zhang, Weidong, Mask creation with hierarchy management using cover cells.
  12. Weber, Wolf-Dietrich; Wingard, Drew E.; Hamilton, Stephen W.; Seigneret, Frank, Method and apparatus for a configurable protection architecture for on-chip systems.
  13. Chou,Chien Chun; Tomlinson,Jay Scott; Weber,Wolf Dietrich; Wingard,Drew Eric; Kasetti,Sricharan, Method and apparatus for configurable address mapping and protection architecture and hardware for on-chip systems.
  14. Ang,Roger P.; McElvain,Ken R.; McElvain,Kenneth S., Method and apparatus for placement and routing cells on integrated circuit chips.
  15. Kerzman, Joseph Peter; Rezek, James Edward, Method and apparatus for selecting and aligning cells using a placement tool.
  16. Betz, Vaughn; Pantofaru, Caroline; Swartz, Jordan, Method and apparatus for utilizing constraints for the routing of a design on a programmable logic device.
  17. Betz, Vaughn; Pantofaru, Caroline; Swartz, Jordan, Method and apparatus for utilizing constraints for the routing of a design on a programmable logic device.
  18. Betz, Vaughn; Pantofaru, Caroline; Swartz, Jordan, Method and apparatus for utilizing constraints for the routing of a design on a programmable logic device.
  19. Rao, Guruprasad G.; Hahn, Mark; Volpe, Laurent, Method and mechanism for implementing region query using hierarchical grids.
  20. Hahn, Mark; Volpe, Laurent; Rao, Guruprasad G., Method and mechanism for maintaining existence information for electronic layout data.
  21. Rao, Guruprasad G.; Hahn, Mark; Volpe, Laurent, Method and mechanism for managing hierarchical data for implementing region query.
  22. Rao, Guruprasad G.; Hahn, Mark; Volpe, Laurent, Method and mechanism for performing region query using hierarchical grids.
  23. Wadland, Ken; Horlick, Greg; Lawson, Randall, Method and system for adaptive bundling of connections in user-guided autorouting.
  24. Boose, John H., Method and system for keyboard managing and navigating among drawing objects.
  25. Chuang, Yi-Lin; Chen, Huang-Yu; Lee, Yun-Han, Method for displaying timing information of an integrated circuit floorplan in real time.
  26. Weber, Wolf-Dietrich; Wingard, Drew A; Hamilton, Stephen W; Seigneret, Frank, Methods and apparatus for a configurable protection architecture for on-chip systems.
  27. Ginetti, Arnold, Methods, systems, and computer program product for dynamically abstracting virtual hierarchies for an electronic design.
  28. Ginetti, Arnold, Methods, systems, and computer program product for implementing dynamic maneuvers within virtual hierarchies of an electronic design.
  29. Wheeler,William R.; Adiletta,Matthew J.; Clark,Christopher; Fennel,Timothy J., Model-based logic design.
  30. Wheeler,William R.; Fennell,Timothy J., Modeling a logic design.
  31. Wolrich,Gilbert; Adiletta,Matthew J.; Gorius,Aaron; Hooper,Donald F.; Carrigan,Douglass; Vora,Chandra, Network device switch.
  32. Mbouombouo, Benjamin; Sabada, Sudhakar, Optimized metal stack strategy.
  33. Ang, Roger P.; McElvain, Ken R.; McElvain, Kenneth S., Placement and routing cells on integrated circuit chips.
  34. Ming, Jian, Real-time display of electronic device design changes between schematic and/or physical representation and simplified physical representation of design.
  35. Fennell, Timothy J.; Wheeler, William R., Representing a simulation model using a hardware configuration database.
  36. Kayser, Joerg; Kohler, Helmut; Schumacher, Norbert, Retrieving odd net topology in hierarchical circuit designs.
  37. Wheeler,William R.; Adiletta,Matthew J., Simulating a logic design.
  38. Stroomer,Jeffrey D.; Milne,Roger B.; Ballagh,Jonathan B.; Ma,Haibing; Hwang,L. James; Shirazi,Nabeel, Specification of the hierarchy, connectivity, and graphical representation of a circuit design.
  39. Frank,Mark D.; Nelson,Jerimy; Bois,Kari, System and method for determining signal coupling coefficients for lines.
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