IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0789027
(1997-01-27)
|
발명자
/ 주소 |
- Garnett, Robert E.
- Kerzman, Joseph P.
- Rezek, James E.
- Aubel, Mark D.
|
출원인 / 주소 |
|
대리인 / 주소 |
Johnson, Charles A.Starr, Mark T.Nawrocki, Rooney & Sivertson P.A.
|
인용정보 |
피인용 횟수 :
39 인용 특허 :
36 |
초록
▼
A method and apparatus for selectively viewing nets within a database editor tool. The present invention provides four primary features for selectively viewing nets. First, the present invention contemplates selecting a number of objects, and viewing only those nets that are either driven from or re
A method and apparatus for selectively viewing nets within a database editor tool. The present invention provides four primary features for selectively viewing nets. First, the present invention contemplates selecting a number of objects, and viewing only those nets that are either driven from or received by the selected objects. In a preferred embodiment, the number of objects are placed objects within a placement tool. Second, for those nets that are selected, and that are also coupled to un-placed cells, the present invention contemplate providing fly-wires from the corresponding selected objects to a predetermined location representative of an approximate expected location for the un-placed cells. Third, the present invention contemplate providing a vector filter which may permit only vectored nets with a selected bus width range to be viewed. Finally, the fourth feature of the present invention contemplates providing a means for selectively viewing only those nets that cross a predetermined hierarchical boundary within the circuit design database.
대표청구항
▼
A method and apparatus for selectively viewing nets within a database editor tool. The present invention provides four primary features for selectively viewing nets. First, the present invention contemplates selecting a number of objects, and viewing only those nets that are either driven from or re
A method and apparatus for selectively viewing nets within a database editor tool. The present invention provides four primary features for selectively viewing nets. First, the present invention contemplates selecting a number of objects, and viewing only those nets that are either driven from or received by the selected objects. In a preferred embodiment, the number of objects are placed objects within a placement tool. Second, for those nets that are selected, and that are also coupled to un-placed cells, the present invention contemplate providing fly-wires from the corresponding selected objects to a predetermined location representative of an approximate expected location for the un-placed cells. Third, the present invention contemplate providing a vector filter which may permit only vectored nets with a selected bus width range to be viewed. Finally, the fourth feature of the present invention contemplates providing a means for selectively viewing only those nets that cross a predetermined hierarchical boundary within the circuit design database. for a building code. 5. The method of claim 1, wherein said created report of step E includes the analysis of the created new project or existing project to demonstrate compliance with the selected standard. a design test for a semiconductor fabrication system, the design test determining a particular value for a parameter associated with a design rule, the particular value being associated with a device failure on a wafer, the wafer comprising: a plurality of memory units, the units each being associated with an associated value for the parameter, wherein the associated value varies across a range for the units, wherein the design test allows the particular value to be determined in response to data associated with the units. 11. The wafer of claim 10, wherein the units are arranged in rows and columns, the units in a particular row or column being associated with the parameter. 12. The wafer of claim 11, wherein the units are comprised of a four-by-four memory cell array. 13. The wafer of claim 12, wherein the units are arranged in four matrices. 14. The wafer of claim 13, wherein the matrices are orthogonally oriented with respect to each other. 15. A method of testing a design rule for an integrated circuit, the integrated circuit including a plurality of memory units, the units being arranged in a plurality of rows and a plurality of columns, wherein the units in a particular row or a particular column are associated with a particular design rule, wherein a parameter associated with the design rule varies from a first end to a second end of the particular row or column, the method comprising: providing data to the units; receiving the data from the units; analyzing the data to determine if a unit has failed; and determining the parameter associated with the failed unit in response to the data by identifying the failed unit. 16. The method of claim 15 further comprising: providing second data to the units; receiving the second data from the units, wherein the analyzing step includes analyzing the second data. 17. The method of claim 15, wherein the analyzing step further includes filtering the data to determine adjacent failed units. 18. The method of claim 15, wherein the units each include a four-by-four array of SRAM devices. 19. The method of claim 18, wherein the failed unit has more than five failed devices. 20. The method of claim 15, wherein the design rule is related to lithographic spacing. 21. A variable design rule tool, comprising: a matrix of units having a plurality of rows and columns, the matrix being disposed on a substrate, wherein the units in a particular row or column are associated with a fabrication design rule, wherein a parameter associated with the design rule varies at a first end of the row or column to the second end of the row or column; an interface couplable to the matrix, the interface receiving digital data associated with the units; and a program receiving the digital data from the interface, the program determining a failure point associated with the parameter in response to the digital data. e is aligned relative to said optical device; etching an orthogonal U-groove at the end of said first U-groove, to provide a glue receptacle, the orthogonal U-groove at the end of the first U-groove being substantially parallel with the at least two second U-grooves; and disposing the optical fibre in the first U-groove and fixing said fibre in said first U-groove. 2. A device which includes at least one optical fibre disposed on a substrate and aligned with at least one optical device, wherein the optical fibre is disposed and fixed in a first U-groove whose walls and end surfaces are essentially vertical in relation to a substrate surface and whose bottom surface is essentially parallel with a nonetched substrate surface, wherein at least two second U-grooves are arranged along the length of, and orthogonal to, the first U-groove, wherein an orthogonal U-groove is provided at the end of the first U-groove and forms a glue receptacle, the U-groove provided at the end of the first U-groove being substantially parallel to the at least two second U-grooves. Enterprise TM 10000 Server, Sun Microsystems, Sep. 1998. Alan Charlesworth, Starfire: Extending the SMP Envelope, IEEE Micro, Jan./Feb. 1998, pp. 39-49. Joseph Heinrich, Origin TM and Onyz2 TM Theory of Operations Manual, Document No. 007-3439-002, Silicon Graphics, Inc., 1997. White Paper, Sequent's NUMA-Q SMP Architecture, Sequent, 1997. White Paper, Eight-way Multiprocessing, Hewlett-Packard, Nov. 1997. George White & Pete Vogt, Profusion, a Buffered, Cache-Coherent Crossbar Switch, presented at Hot Interconnects Symposium V, Aug. 1997. Alan Charlesworth, et al., Gigaplane--XB: Extending the Ultra Enterprise Family, presented at Hot Interconnects Symposium V, Aug. 1997. James Loudon & Daniel Lenoski, The SGI Origin: A ccNUMA Highly Scalable Server, Silcon Graphics, Inc., presented at the Proc. Of the 24thInt'l Symp. Computer Architecture, Jun. 1997. Mike Galles, Spider: A High-Speed Network Interconnect, IEEE Micro, Jan./Feb. 1997, pp. 34-39. T.D. Lovett, R. M. Clapp and R. J. Safranek, NUMA-Q: an SCI-based Enterprise Server, Sequent, 1996. Daniel E. Lenoski & Wolf-Dietrich Weber, Scalable Shared-Memory Multiprocessing, Morgan Kaufmann Publishers, 1995, pp. 143-159. David B. Gustavson, The Scalable coherent Interface and Related Standards Projects, (as reprinted in Advanced Multimicroprocessor Bus Architectures, Janusz Zalewski, IEEE computer Society Press, 1995, pp. 195-207.). Kevin Normoyle, et al., UltraSPARC TM Port Architecture, Sun Microsystems, Inc., presented in Hot Interconnects III, Aug. 1995. Kevin Normoyle, et al., UltraSPARC TM Port Architecture, Sun Microsystems, Inc., presented in Hot Interconnects III, Aug. 1995, UltraSparc Interfaces. Kai Hwang, Advanced Computer Architecture: Parallelism Scalability, Programmability, McGraw-Hill, 1993, pp. 355-357. Jim Handy, The Cache Memory Book, Academic Press, 1993, pp. 161-169. Angel L. Decegama, Parallel Processing Architectures and VLSI Hardware, vol. 1, Prentice-Hall, 1989, pp. 341-344. us data into a plurality of different data groups and pre-allocating each of the data groups to a corresponding one of a plurality of storage areas in the volatile memory and in the nonvolatile memory, wherein the saving of each data group to the nonvolatile memory is responsive to at least one of a plurality of trigger events, and wherein at least two of the data groups do not have any common trigger events; and (b) generating a command to save a select number of data groups from the volatile memory to the nonvolatile memory when any one of the trigger events to which the data group or groups to be saved is/are responsive occurs; and (c) saving a particular data group stored in its pre-allocated storage area in the volatile memory to its corresponding storage area in the nonvolatile memory in response to the generated save command when any one of the plurality of trigger events to which that data group is responsive occurs. 2. The method as set forth in claim 1, wherein the plurality of trigger events includes detection of a reset signal from a host computer, and wherein the method further comprises the step of: (d) resetting the printer based on the detected reset signal after performing step (c). 3. The method as set forth in claim 1, wherein the plurality of trigger events includes lapse of a specific time interval, turning printer power on or off, and specific control events in printer operation. 4. The method as set forth in claim 3, wherein the specific control events in printer operation include print head cleaning. 5. The method as set forth in claim 1, wherein each storage area further contains an error detection code, and the method further comprises the step of: (d) checking for errors in each data group using the error detection code in the corresponding storage area. 6. The method as set forth in claim 5, wherein step (d) further comprises checking for errors in a particular data group when that data group is read from the nonvolatile memory and temporarily stored in the volatile memory. 7. The method as set forth in claim 5, wherein step (d) further comprises checking for errors in a particular data group after that data group is written to the nonvolatile memory from the volatile memory. 8. The method as set forth in claim 5, further comprising the step of: (e) writing specific initialization data to each storage area in the volatile memory and the nonvolatile memory from which an error-detected data group is read or to which an error-detected data group is written. 9. A method for controlling the saving of information regarding operating conditions in a printer that comprises a nonvolatile memory for storing printer status data relating to the printer operating conditions, and a volatile memory for temporarily storing the printer status data, said method comprising the steps of: (a) grouping the printer status data into a plurality of different data groups and pre-allocating each of the data groups to a corresponding one of a plurality of storage areas in the volatile memory and in the nonvolatile memory, wherein the saving of each data group to the nonvolatile memory is responsive to at least one of a plurality of trigger events, the plurality of trigger events including lapse of a specific time interval, turning printer power on or off, and specific control events in printer operation; and (b) generating a command to save a select number of data groups from the volatile memory to the nonvolatile memory when any one of the trigger events occurs; and (c) saving a particular data group stored in its pre-allocated storage area in the volatile memory to its corresponding storage area in the nonvolatile memory in response to the generated save command when any one of the plurality of trigger events to which that data group is responsive occurs, wherein the printer status data is pre-divided into a first data set comprising at least one data group and a second data set comprising at least
※ AI-Helper는 부적절한 답변을 할 수 있습니다.