$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Semiconductor device and method for manufacturing 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
  • H01L-021/48
  • H01L-021/50
출원번호 US-0794108 (2001-02-28)
우선권정보 JP-0213174 (2000-07-13); JP-0316592 (2000-10-17)
발명자 / 주소
  • Kikuchi, Hidekazu
출원인 / 주소
  • Oki Electric Industry Co., Ltd.
대리인 / 주소
    Rabin & Berdo, P.C.
인용정보 피인용 횟수 : 70  인용 특허 : 8

초록

A semiconductor device which has trenches for raising the reliability thereof and a method for manufacturing such device. An electrode pad, and a protective film and an interlayer film which comprise an opening on top of this electrode pad, are formed on a substrate. A rewiring pattern which is in c

대표청구항

A semiconductor device which has trenches for raising the reliability thereof and a method for manufacturing such device. An electrode pad, and a protective film and an interlayer film which comprise an opening on top of this electrode pad, are formed on a substrate. A rewiring pattern which is in c

이 특허에 인용된 특허 (8)

  1. Kim Sam Il,KRX ; Cho Young Rae,KRX, Chip-size packages assembled using mass production techniques at the wafer-level.
  2. Hashimoto Nobuaki,JPX, Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument.
  3. Chen Ming Hsien,TWX ; Li Mei-Yen,TWX ; Chen Li-Don,TWX ; Chen Chih-Ming,TWX, Method of assembly stress protection.
  4. Hundt Michael J., Packaging for silicon sensors.
  5. Hashimoto Nobuaki,JPX, Semiconductor device and method of making the same, circuit board, and electronic instrument.
  6. Morita Naoyuki (Naganoken JPX) Tsugane Hiroaki (Naganoken JPX), Semiconductor device chip with interlayer insulating film covering the scribe lines.
  7. Sauber John B. ; Kowaleski ; Jr. John A. ; Maggard Jeffrey G., Semiconductor structures and packaging methods.
  8. Schaefer William Jeffrey ; Kao Pai-Hsiang ; Kelkar Nikhil Vishwanath, Surface mount die: wafer level chip-scale package and process for making the same.

이 특허를 인용한 특허 (70)

  1. Lin, Mou-Shiung; Chou, Chiu-Ming, Chip structure.
  2. Lin, Mou-Shiung; Chou, Chiu-Ming, Chip structure.
  3. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  4. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  5. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip structure and process for forming the same.
  6. Lin, Mou-Shiung; Chou, Chien-Kang; Chen, Ke-Hung, Circuitry component and method for forming the same.
  7. Lee, Jin-Yuan; Chou, Chien-Kang; Lin, Shih-Hsiung; Kuo, Hsi-Shan, Cylindrical bonding structure and method of manufacture.
  8. Wenzel, Robert J.; Leal, George R., Fine pitch interconnect and method of making.
  9. Lin, Mou-Shing, High performance system-on-chip using post passivation process.
  10. Lin, Mou-Shiung, High performance system-on-chip using post passivation process.
  11. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  12. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  13. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  14. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  15. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  16. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  17. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Low fabrication cost, fine pitch and high reliability solder bump.
  18. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Low fabrication cost, fine pitch and high reliability solder bump.
  19. Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng; Lin, Chuen-Jye, Low fabrication cost, high performance, high reliability chip scale package.
  20. Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng; Lin, Chuen-Jye, Low fabrication cost, high performance, high reliability chip scale package.
  21. Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng; Lin, Chuen-Jye, Low fabrication cost, high performance, high reliability chip scale package.
  22. Happer, William; Walter, Daniel K., Method and system for operating an atomic clock with reduced spin-exchange broadening of atomic clock resonances.
  23. Lee, Jin-Yuan; Chou, Chien-Kang; Lin, Shih-Hsiung; Kuo, Hsi-Shan, Method for fabricating circuit component.
  24. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Method for fabricating circuitry component.
  25. Hiatt,William M.; Farnworth,Warren M.; Watkins,Charles M.; Sinha,Nishant, Method for fabricating semiconductor components having encapsulated, bonded, interconnect contacts on redistribution contacts.
  26. Liu, Hsien-Tsung; Chou, Chien-Kang; Lin, Ching-San, Method of metal sputtering for integrated circuit metal routing.
  27. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection process and structures.
  28. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection process and structures.
  29. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  30. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  31. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  32. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  33. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  34. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  35. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chips.
  36. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
  37. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
  38. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection structures.
  39. Lin, Mou-Shiung; Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng, Post passivation metal scheme for high-performance integrated circuit devices.
  40. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation method for semiconductor chip or wafer.
  41. Lin, Mou-Shiung; Chou, Chien-Kang; Chen, Ke-Hung, Post passivation structure for a semiconductor device and packaging process for same.
  42. Huang, Ching-Cheng; Lin, Chuen-Jye; Lei, Ming-Ta; Lin, Mou-Shiung, Reliable metal bumps on top of I/O pads after removal of test probe marks.
  43. Ohsumi,Takashi, Semiconductor device having chip size package with improved strength.
  44. Chen, Hsien-Wei; Yeh, Der-Chyang; Huang, Li-Hsien, Stacked semiconductor devices and methods of forming same.
  45. Lin, Mou-Shiung; Lei, Ming-Ta; Lin, Chuen-Jye, Structure and manufacturing method of a chip scale package.
  46. Chou, Chiu-Ming; Lin, Mou-Shiung, Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures.
  47. Hiatt,William M.; Farnworth,Warren M.; Watkins,Charles M.; Sinha,Nishant, System having semiconductor component with encapsulated, bonded, interconnect contacts.
  48. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  49. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  50. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  51. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  52. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  53. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  54. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  55. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  56. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  57. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  58. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  59. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  60. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  61. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  62. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  63. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  64. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  65. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  66. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  67. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  68. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  69. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  70. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로