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In a pixel having an electronic shutter, a method of increasing the retention time of the electronic shutter is disclosed. A reset signal is employed to drive a diode node to a predetermined voltage immediately after integration is completed. A sample signal is employed to control a pass gate. The s

In a pixel having an electronic shutter, a method of increasing the retention time of the electronic shutter is disclosed. A reset signal is employed to drive a diode node to a predetermined voltage immediately after integration is completed. A sample signal is employed to control a pass gate. The sample signal includes a state where the sample signal is a negative voltage.

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1. In a pixel having an electronic shutter, a method of increasing the retention time of the electronic shutter comprising: a) employing a reset signal to drive a diode node to a predetermined voltage immediately after an integration is complete and during readout, and to substantially inhibit su

1. In a pixel having an electronic shutter, a method of increasing the retention time of the electronic shutter comprising: a) employing a reset signal to drive a diode node to a predetermined voltage immediately after an integration is complete and during readout, and to substantially inhibit subthreshold leakage from a storage node; and b) employing a sample signal to control a pass gate, said sample signal having a state where said sample signal is a negative voltage. 2. The method of claim 1 further comprising: employing metal to shield a source node of the pass gate. 3. A pixel controller comprising: a) a reset generator for providing a reset signal to control a first transistor and for driving the reset signal to a predetermined voltage immediately after integration is complete; and b) a sample signal generator, for providing a sample signal to control a pass gate. 4. The pixel controller of claim 3 further comprising: a row signal generator for generating a row signal that selectively reads out a value on the storage node and selectively provides said value to a bitline. 5. In an image capture system including a pixel, said pixel having a first node and a second node, a method of increasing the retention time of a pixel value on the second node, said method comprising: a) asserting a reset signal to reset a first node to a predetermined value; b) asserting a sample signal for a predetermined integration time to store a pixel value on the second node; c) driving said sample signal to a negative voltage after said predetermined integration time; and d) asserting said reset signal after said sample signal is driven to said negative voltage; wherein asserting said reset signal and driving of said sample signal to said negative voltage continues throughout the readout period. 6. The method of claim 5 further comprising: reading out the pixel values. 7. The method of claim 5 further comprising: reading out a first row of pixels. 8. The method of claim 7 further comprising: reading out a second row of pixels. 9. The method of claim 5 wherein the image capture system is operating in a frame mode. 10. The method of claim 5 wherein the image capture system is operating in a row mode. 11. A method of frame mode operation of a pixel array, said array having a plurality of pixel cells, each pixel cell having a reset transistor for receiving a reset signal, a sample transistor for receiving a sample signal, said method comprising: a) asserting a reset signal; b) asserting a sample signal; c) deasserting the reset signal to begin integration; d) deasserting the sample signal to stop integration and driving said sample signal to a negative voltage; e) asserting the reset signal immediately after the sample signal is deasserted; and f) reading out a pixel value for a first row.