초록 ▼

The present invention discloses a combination media and media station storage unit for storing a multiplicity of media elements along with a media station for the media elements. The combination unit allows a media station to be stored and secured for protection while allowing connections for signal

The present invention discloses a combination media and media station storage unit for storing a multiplicity of media elements along with a media station for the media elements. The combination unit allows a media station to be stored and secured for protection while allowing connections for signals and allowing controls for the media station to be accessed while it is in a stored and secure position. The combination media and media station storage unit also has removable lids that may contain optional features for adding functionality to the combination media and media station storage unit. These features include but are not limited to speakers, electronics for remote broadcast of playback information, electronics for remote control of the media station, batteries, windows for observing media station status, etc. The combination unit also includes features for attaching a shoulder strap and a leg strap that enables a user to walk or jog while playing media and keeping the combination unit secure and stationary. The shoulder strap also has the audio cable for the headset integrated eliminating long headset cabling.

대표청구항 ▼

The present invention discloses a combination media and media station storage unit for storing a multiplicity of media elements along with a media station for the media elements. The combination unit allows a media station to be stored and secured for protection while allowing connections for signal

The present invention discloses a combination media and media station storage unit for storing a multiplicity of media elements along with a media station for the media elements. The combination unit allows a media station to be stored and secured for protection while allowing connections for signals and allowing controls for the media station to be accessed while it is in a stored and secure position. The combination media and media station storage unit also has removable lids that may contain optional features for adding functionality to the combination media and media station storage unit. These features include but are not limited to speakers, electronics for remote broadcast of playback information, electronics for remote control of the media station, batteries, windows for observing media station status, etc. The combination unit also includes features for attaching a shoulder strap and a leg strap that enables a user to walk or jog while playing media and keeping the combination unit secure and stationary. The shoulder strap also has the audio cable for the headset integrated eliminating long headset cabling. nic timepiece has a temperature compensation function for the reference oscillator, and said condition-varying means is a temperature-varying device. 5. A data transmission/reception system for an electronic timepiece comprising: a data transmission/reception device which receives a timing signal from an electronic timepiece, generates a data signal in response to said timing signal that is received, and transmits said data signal to the electronic timepiece; said electronic timepiece equipped with transmission/reception means for transmitting the timing signal to said data transmission/reception device, and for receiving said data signal from said data transmission/reception device; condition-varying means for giving changes in external conditions to said electronic timepiece; timing signal-generating means in said electronic timepiece for outputting said timing signal; timing signal-receiving means in said data transmission/reception device for receiving the timing signal from the transmission/reception means of said electronic timepiece; and means in said data transmission/reception device for transmitting said data signal to said electronic timepiece after detecting the timing signal received from the electronic timepiece, and for controlling the condition setting of the condition-varying means. said third internal clock signal to said second interface circuit. 4. The semiconductor memory device according to claim 3, further comprising an internal circuit performing write operations on said input data in synchronization with an operational clock, a buffer circuit supplying said operational clock to said internal circuit, and a switch circuit selectively providing one of said first source clock signal and said third internal clock signal to said buffer circuit. 5. The semiconductor memory device according to claim 2, wherein said first internal clock signal has a higher frequency than the frequency of said first external clock signal, said third interface circuit further includes a data output circuit outputting output data in synchronization with said first internal clock signal, and the semiconductor memory device further comprises a strobe signal output circuit outputting a strobe signal in synchronization with said first internal clock signal. 6. A semiconductor memory device comprising: a first interface circuit receiving a first external clock signal and a second external clock signal complementary to said first external clock signal from the outside of said semiconductor memory device, said first interface circuit including a comparator generating a first source clock signal by comparing said first external clock signal with a reference voltage in a first operation mode, and generating a second source clock signal and a third source clock signal complementary to said second source clock signal by comparing said first external clock signal with said second external clock signal in a second operation mode, and a switch circuit selectively providing one of said second external clock signal and said reference voltage to said comparator according to which one of said first and second operation modes is designated; and an internal clock generation circuit generating an internal clock signal for data output operation based on said first source clock signal in said first operation mode, and generating said internal clock signal based on said second and third source clock signals in said second operation mode. 7. A semiconductor memory device comprising: a first interface circuit receiving a first external clock signal and a second external clock signal complementary to said first external clock signal from the outside of said semiconductor memory device, said first interface circuit including a comparator generating a first source clock signal by comparing said first external clock signal with a reference voltage in a first operation mode, and generating a second source clock and a third source clock signal complementary to said second source clock signal by comparing said first external clock signal with said second external clock signal in a second operation mode; an internal clock generation circuit generating a first internal clock signal for data output operation based on said first source clock signal in said first operation mode, and generating a second internal clock signal for data output operation based on said second and third source clock signals in said second operation mode; a second interface circuit including a data output circuit outputting output data in synchronization with said first internal clock signal in said first operation mode and in synchronization with said second internal clock signal in said second operation mode; and a strobe signal output circuit outputting a strobe signal in synchronization with said second internal clock signal in said second operation mode. hes a read command and a write command; second pins supplied with upper-side and lower-side decode addresses; a controller to which a signal indicating that the read command is input and a signal indicating that the write command is input based on the signal input to said first pin are supplied; a first command decoder controlled by an output signal of said controller, which defines the readout/write operation by use of the first command, fetches an upper-side decode address of a memory cell array via said second pin and decodes the first command; and a lower-side command decoder controlled by an output signal of said controller, which fetches a lower-side decode address of the memory cell array via the control pin in response to the second command, decodes the lower-side command and outputs a lower address latch command, mode register set command and auto-refresh command. 2. The semiconductor memory device according to claim 1, wherein existing pins are also used as said second pins. 3. The semiconductor memory device according to claim 2, wherein said existing pins are a write enable pin and column address strobe pin in an SDR-SDRAM or DDR-SDRAM. 4. The semiconductor memory device according to claim 1, further comprising a gating signal generating circuit which controls activation of a column selection line to permit the shortest time required for amplifying random readout data from the memory cell array to occur later than a period of time from when the second command is supplied until the column selection line is selected. 5. The semiconductor memory device according to claim 4, which further comprises a column decoder supplied with a column address signal and a gating signal output from said gating signal generating circuit, said column decoder outputting a column selection signal to the column selection line and in which activation of the column selection line is controlled by the gating signal.