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A semiconductor projection is formed on a semiconductor substrate of the first conductivity type and has a semiconductor layer of the first conductivity type. The semiconductor projection has a top surface and side surfaces. A gate electrode is formed above at least the side surfaces of the semicond

A semiconductor projection is formed on a semiconductor substrate of the first conductivity type and has a semiconductor layer of the first conductivity type. The semiconductor projection has a top surface and side surfaces. A gate electrode is formed above at least the side surfaces of the semiconductor projection. Source and drain regions are formed in the side surfaces of the semiconductor projection on opposite sides of the gate electrode. First and second device isolation insulating films are formed on the semiconductor substrate on opposite sides of the semiconductor projection. A first impurity region is formed in the semiconductor substrate below the first device isolation insulating film. A second impurity region is formed in the semiconductor substrate below the second device isolation insulating film. The first and second impurity regions are in contact with each other in the semiconductor substrate below the semiconductor projection.

대표청구항 ▼

A semiconductor projection is formed on a semiconductor substrate of the first conductivity type and has a semiconductor layer of the first conductivity type. The semiconductor projection has a top surface and side surfaces. A gate electrode is formed above at least the side surfaces of the semicond

A semiconductor projection is formed on a semiconductor substrate of the first conductivity type and has a semiconductor layer of the first conductivity type. The semiconductor projection has a top surface and side surfaces. A gate electrode is formed above at least the side surfaces of the semiconductor projection. Source and drain regions are formed in the side surfaces of the semiconductor projection on opposite sides of the gate electrode. First and second device isolation insulating films are formed on the semiconductor substrate on opposite sides of the semiconductor projection. A first impurity region is formed in the semiconductor substrate below the first device isolation insulating film. A second impurity region is formed in the semiconductor substrate below the second device isolation insulating film. The first and second impurity regions are in contact with each other in the semiconductor substrate below the semiconductor projection. a third impurity layer being of a conductive type different from that of the first impurity layer; a fourth impurity layer being of a conductive type identical to that of the first impurity layer; wherein the second impurity layer, the third impurity layer and the fourth impurity layer are formed such that: the second impurity layer is formed so as to be under and extending outwardly beyond the first impurity layer, the third impurity layer is formed under a portion of the second impurity layer and not formed under another portion of the second impurity layer so as to exclude at least a part of a non-imaging region, and the fourth impurity layer is formed so a portion thereof is under the third impurity layer and so another portion thereof is under the said another portion of the second impurity layer; and a fifth impurity layer being formed under the fourth impurity layer, being of a conductive type identical to that of the fourth impurity layer and having an impurity concentration higher than that of the fourth impurity layer. 2. A solid-state imaging device as claimed in claim 1, wherein the fourth impurity layer and the fifth impurity layer are continuously formed by varying a gas flow rate in one epitaxial growth process. 3. A solid-state imaging device as claimed in claim 1, wherein the fifth impurity layer has an impurity concentration of not lower than 5×1015cm-3. 4. A solid-state imaging device as claimed in claim 1, wherein the second impurity layer is formed by low pressure epitaxial growth whose growth temperature is higher than 1050° C. and lower than 1150° C. 5. A solid-state imaging device as claimed in claim 1, wherein the second impurity layer is formed by atmospheric pressure epitaxial growth whose growth temperature is not lower than 1150° C. 6. A solid-state imaging device as claimed in claim 1, wherein the second impurity layer has an impurity concentration of not higher than 1×1014cm-3. 7. A solid-state imaging device as claimed in claim 1, wherein the first impurity layer and the second impurity layer have impurity concentrations differing from each other by two or more orders of magnitude, and the impurity concentration of the first impurity layer is set higher than the impurity concentration of the second impurity layer. at terminal connection points and arranged in at least one first wiring layer over the semiconductor substrate, the terminal wires having thereon a plurality of terminal wire connection points for connecting with circuit wires to be formed in at least one second wiring layer above the first wiring layer, wherein at least one of the terminal wires is connected to one or more of the terminals at only one of the terminal connection points and has thereon at least two of the terminal wire connection points. 2. The basic cell according to claim 1, wherein at most one of the terminal connection points is provided for each of the terminals of the transistors. 3. The basic cell according to claim 1, wherein the at least two of the terminal wire connection points of the at least one of the terminal wires are arranged two-dimensionally. 4. The basic cell according to claim 1, wherein the terminal wire connection points are arranged on grid points with a fixed pitch, and at least some of the terminal connection points are displaced from the grid points. 5. The basic cell according to claim 1, wherein the first wiring layer is a low resistance metal wiring. layer. 6. A semiconductor integrated circuit, comprising: a cell array including a plurality of basic cells, each of the basic cells including a plurality of transistors arranged on a semiconductor substrate and a plurality of teal wires formed in at least one first wiring layer over the semiconductor substrate, the transistors including a plurality of terminals and the terminal wires being connected to the terminals at terminal connection points; and a plurality of Circuit wires formed in at least one second wiring layer above the first wiring layer, and connected to respective terminal wires, wherein the terminal wires have thereon a plurality of terminal wire connection points for connecting with the circuit wires, and at least one of the terminal wires is connected to at least one of the terminals of the transistors at only one of the terminal connection points and has thereon at least two of the terminal wire connection points. 7. The semiconductor integrated circuit according to claim 6, wherein the circuit wires are arranged along grid points with a fixed pitch, and at least some of the terminal connection points are displaced from the grid points. 8. The semiconductor integrated circuit according to claim 6, wherein the at least two of the terminal wire connection points of the at least one of the terminal wires are arranged two-dimensionally. 9. A semiconductor integrated circuit, comprising: a cell array area including an array of basic cells arranged on a semiconductor substrate, each of the basic cells including a plurality of transistors having a plurality of terminals and a plurality of terminal wires formed in at least one first wiring layer over the semiconductor substrate, the terminals of the transistors having thereon terminal connection points; and a plurality of circuit wires formed in at least one second wiring layer above the first wiring layer, each of the circuit wires having at least one circuit connection point arranged on grid points, wherein: the transistors in each of the basic cells include k gate electrodes generally extending in a first direction and arranged in a second direction perpendicular to the first direction, and k+1 diffusion regions on both sides of the k gate electrodes, where k is an integer greater than one; the array of basic cells includes two adjacent ones of the basic cells arranged in the second direction; the grid points are arranged in the second direction with a first fixed pitch; and at least one of the terminal connection points connecting to the diffusion regions is displaced from the grid points such that the terminal connection points connecting to 2k+2 diffusion regions of the two adjacent ones of the basic cells are arranged in the second direction with a second fixed pitch larger than the first fixed pit ch, and the displaced terminal connection point is connected to one of the circuit connection points through a corresponding one of the terminal wires. 10. The semiconductor integrated circuit according to claim 9, wherein the transistors in each of the basic cells include gate electrodes generally extending in a first direction and arranged in a second direction perpendicular to the first direction, and the displaced terminal connection point is displaced from the grid points at least in the second direction. 11. A semiconductor integrated circuit comprising: a cell array area including an array of basic cells arranged on a semiconductor substrate, each of the basic cells including a plurality of transistors having a plurality of terminals and a plurality of terminal wires formed in at least one first wiring layer over the semiconductor substrate, the terminals of the transistors having thereon terminal connection points; and a plurality of circuit wires formed in at least one second wiring layer above the first wiring layer, each of the circuit wires having at least one circuit connection point arranged on grid points, wherein: at least one of the terminal connection points is displaced from the grid points; and the displaced terminal connection point is connected to one of the circuit connection points through a corresponding one of the terminal wires having thereon a terminal wire connection point displaced from the grid points, and a terminal wire connection element extending in the second wiring layer between a position above the displaced terminal wire connection point to the one of the circuit connection points. 12. The semiconductor integrated circuit according to claim 11, wherein each of the terminal wires is connected to only one of the terminal connection points. 13. The semiconductor integrated circuit according to claim 11, wherein the terminal connection points are connected to the respective circuit connection points always through the respective terminal wires. 14. A semiconductor integrated circuit, comprising: a cell array including a plurality of basic cells arranged on a semiconductor substrate along a first direction with a pitch Pc,each of the basic cells including a plurality of transistors; and a plurality of circuit wires over the cell array, the circuit wires being placed on grid lines perpendicular to the first direction, the grid lines being arranged with a pitch Pwin the first direction, wherein Pcis not an integral multiple of Pw,and Pc×nis equal to Pw×m,where each of m and n is an integer greater than one. 15. The semiconductor integrated cit according to claim 14, wherein each of the basic cells includes k gate electrodes generally extending perpendicular to the first direction and arranged in the first direction, where k in an integer greater than one, and m is greater than (k+1)×n. 16. A semiconductor integrated circuit, comprising: a cell array including a plurality of basic cells arranged on a semiconductor substrate along a first direction, each of the basic cells including a plurality of transistors; a plurality of circuit wires over the cell array, the circuit wires being placed on grid lines perpendicular to the first direction, wherein: the grid lines have a first fixed pitch in the first direction, and include cell grid lines above the basic cells and boundary grid lines above boundaries between the basic cells; the plurality of basic cells includes two adjacent ones of the basic cells on both sides of one of the boundary grid lines; each one of the basic cells includes k gate electrodes generally extending to a second direction perpendicular to the first direction and arranged in the first direction, and k+1 diffusion regions on both sides of the k gate electrodes, where k is an integer greater than one; and 2k+2 contacts to connect to the diffusion regions of the two adjacent ones of